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Searched refs:mmSH_MEM_CONFIG (Results 1 – 17 of 17) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v7.c253 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings()
Damdgpu_amdkfd_gfx_v8.c209 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings()
Damdgpu_amdkfd_gfx_v9.c141 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
Damdgpu_amdkfd_gfx_v10.c230 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_program_sh_mem_settings()
Dsoc15.c433 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) in soc15_program_register_sequence()
Dgfx_v9_0.c509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
2470 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in gfx_v9_0_init_compute_vmid()
2528 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2535 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
Dgfx_v7_0.c1875 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in gfx_v7_0_init_compute_vmid()
1980 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); in gfx_v7_0_constants_init()
Dgfx_v8_0.c3735 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in gfx_v8_0_init_compute_vmid()
3818 WREG32(mmSH_MEM_CONFIG, tmp); in gfx_v8_0_constants_init()
3825 WREG32(mmSH_MEM_CONFIG, tmp); in gfx_v8_0_constants_init()
Dgfx_v10_0.c1616 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v10_0_init_compute_vmid()
1753 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v10_0_constants_init()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h1945 #define mmSH_MEM_CONFIG 0x230d macro
Dgfx_7_2_d.h1966 #define mmSH_MEM_CONFIG 0x230d macro
Dgfx_8_1_d.h2133 #define mmSH_MEM_CONFIG 0x230d macro
Dgfx_8_0_d.h2165 #define mmSH_MEM_CONFIG 0x230d macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h408 #define mmSH_MEM_CONFIG macro
Dgc_9_1_offset.h402 #define mmSH_MEM_CONFIG macro
Dgc_9_2_1_offset.h398 #define mmSH_MEM_CONFIG macro
Dgc_10_1_0_offset.h2448 #define mmSH_MEM_CONFIG macro