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Searched refs:mmJPEG_CGC_CTRL (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h154 #define mmJPEG_CGC_CTRL … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h334 #define mmJPEG_CGC_CTRL … macro
Dvcn_2_5_offset.h353 #define mmJPEG_CGC_CTRL … macro
Dvcn_2_0_0_offset.h350 #define mmJPEG_CGC_CTRL … macro
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_5.c626 tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL); in jpeg_v2_5_start()
630 WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp); in jpeg_v2_5_start()
639 tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL); in jpeg_v2_5_start()
644 WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp); in jpeg_v2_5_start()
Dvcn_v1_0.c446 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
455 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
573 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
580 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
644 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_0.c690 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_start()
694 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); in jpeg_v2_0_start()
746 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_stop()
750 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); in jpeg_v2_0_stop()