| /Linux-v5.4/Documentation/arm64/ |
| D | legacy_instructions.rst | 2 Legacy instructions
6 emulation of instructions which have been deprecated, or obsoleted in
18 Generates undefined instruction abort. Default for instructions that
27 instructions, .e.g., CP15 barriers
34 instructions. Using hardware execution generally provides better
36 about the use of the deprecated instructions.
39 architecture. Deprecated instructions should default to emulation
40 while obsolete instructions must be undefined by default.
45 Supported legacy instructions
|
| D | pointer-authentication.rst | 25 The extension adds instructions to insert a valid PAC into a pointer,
30 A subset of these instructions have been allocated from the HINT
32 these instructions behave as NOPs. Applications and libraries using
33 these instructions operate correctly regardless of the presence of the
58 uses instructions in the HINT space (unless -march=armv8.3-a or higher
108 register. Any attempt to use the Pointer Authentication instructions will
|
| /Linux-v5.4/tools/perf/Documentation/ |
| D | itrace.txt | 1 i synthesize instructions events
20 for instructions events can be specified in units of:
22 i instructions
28 Also the call chain size (default 16, max. 1024) for instructions or
32 instructions or transactions events can be specified.
34 It is also possible to skip events generated (instructions, branches, transactions,
39 skips the first million instructions.
|
| D | tips.txt | 2 Sample related events with: perf record -e '{cycles,instructions}:S'
29 See assembly instructions with percentage: perf annotate <symbol>
42 To show IPC for sampling periods use perf record -e '{cycles,instructions}:S' and then browse conte…
|
| /Linux-v5.4/drivers/watchdog/ |
| D | wdat_wdt.c | 47 struct list_head *instructions[MAX_WDAT_ACTIONS]; member
112 if (action >= ARRAY_SIZE(wdat->instructions)) in wdat_wdt_run_action()
115 if (!wdat->instructions[action]) in wdat_wdt_run_action()
121 list_for_each_entry(instr, wdat->instructions[action], node) { in wdat_wdt_run_action()
370 struct list_head *instructions; in wdat_wdt_probe() local
417 instructions = wdat->instructions[action]; in wdat_wdt_probe()
418 if (!instructions) { in wdat_wdt_probe()
419 instructions = devm_kzalloc(dev, in wdat_wdt_probe()
420 sizeof(*instructions), in wdat_wdt_probe()
422 if (!instructions) in wdat_wdt_probe()
[all …]
|
| /Linux-v5.4/Documentation/bpf/ |
| D | bpf_design_QA.rst | 93 It's the maximum number of instructions that the unprivileged bpf
95 Like the maximum number of instructions that can be explored during
98 of 1 million NOP instructions. There is a limit to the maximum number
119 Q: LD_ABS and LD_IND instructions vs C code
129 Q: BPF instructions mapping not one-to-one to native CPU
131 Q: It seems not all BPF instructions are one-to-one to native CPU.
154 of LD_ABS insn). Those instructions need to invoke epilogue and
157 Q: Why BPF_JLT and BPF_JLE instructions were not introduced in the beginning?
161 due to lack of these compare instructions and they were added.
162 These two instructions is a perfect example what kind of new BPF
[all …]
|
| /Linux-v5.4/Documentation/arm/ |
| D | swp_emulation.rst | 4 ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
5 moving to the load-locked/store-conditional instructions LDREX and STREX.
8 instructions, triggering an undefined instruction exception when executed.
9 Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
|
| D | kernel_mode_neon.rst | 7 * Use only NEON instructions, or VFP instructions that don't rely on support
19 It is possible to use NEON instructions (and in some cases, VFP instructions) in
24 may call schedule()], as NEON or VFP instructions will be executed in a
43 should be called before any kernel mode NEON or VFP instructions are issued.
74 Such software assistance is currently not implemented for VFP instructions
82 kernel_neon_end(), i.e., that it is only allowed to issue NEON/VFP instructions
84 instructions of its own at -O3 level if -mfpu=neon is selected, and even if the
86 instructions appearing in unexpected places if no special care is taken.
98 both NEON and VFP instructions will only ever appear in designated compilation
|
| /Linux-v5.4/arch/arm64/crypto/ |
| D | Kconfig | 8 implemented using ARM64 specific CPU features or instructions.
64 tristate "CRCT10DIF digest algorithm using PMULL instructions"
69 tristate "AES core cipher using scalar instructions"
95 tristate "AES in ECB/CBC/CTR/XTS modes using NEON instructions"
103 tristate "ChaCha20, XChaCha20, and XChaCha12 stream ciphers using NEON instructions"
109 tristate "NHPoly1305 hash function using NEON instructions (for Adiantum)"
|
| /Linux-v5.4/tools/testing/selftests/powerpc/pmu/ |
| D | count_instructions.c | 29 static int do_count_loop(struct event *events, u64 instructions, in do_count_loop() argument
38 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
45 expected = instructions + overhead; in do_count_loop()
53 printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead); in do_count_loop()
|
| /Linux-v5.4/tools/testing/selftests/powerpc/pmu/ebb/ |
| D | instruction_count_test.c | 25 static int do_count_loop(struct event *event, uint64_t instructions, in do_count_loop() argument
37 thirty_two_instruction_loop(instructions >> 5); in do_count_loop()
46 expected = instructions + overhead; in do_count_loop()
51 printf("Looped for %lu instructions, overhead %lu\n", instructions, overhead); in do_count_loop()
|
| /Linux-v5.4/tools/memory-model/ |
| D | linux-kernel.bell | 20 instructions R[{'once,'acquire,'noreturn}]
21 instructions W[{'once,'release}]
22 instructions RMW[{'once,'acquire,'release}]
35 instructions F[Barriers]
39 instructions SRCU[SRCU]
|
| /Linux-v5.4/Documentation/virt/kvm/ |
| D | ppc-pv.txt | 6 instructions and can emulate them accordingly.
9 instructions that needlessly return us to the hypervisor even though they
12 This is what the PPC PV interface helps with. It takes privileged instructions
32 'hypercall-instructions'. This property contains at most 4 opcodes that make
33 up the hypercall. To call a hypercall, just call these instructions.
129 Patched instructions
132 The "ld" and "std" instructions are transformed to "lwz" and "stw" instructions
138 also act on the shared page. So calling privileged instructions still works as
178 Some instructions require more logic to determine what's going on than a load
180 RAM around where we can live translate instructions to. What happens is the
|
| /Linux-v5.4/Documentation/virt/ |
| D | paravirt_ops.rst | 16 corresponding to low level critical instructions and high level
28 Usually these operations correspond to low level critical instructions. They
34 because they include sensitive instructions or some of code paths in
|
| /Linux-v5.4/arch/arm/crypto/ |
| D | Kconfig | 8 implemented using ARM specific CPU features or instructions.
28 using optimized ARM NEON assembly, when NEON instructions are
82 tristate "Bit sliced AES using NEON instructions"
120 tristate "CRCT10DIF digest algorithm using PMULL instructions"
125 tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
|
| /Linux-v5.4/tools/perf/tests/attr/ |
| D | README | 50 perf record --group -e cycles,instructions kill (test-record-group)
51 perf record -e '{cycles,instructions}' kill (test-record-group1)
62 perf stat --group -e cycles,instructions kill (test-stat-group)
63 perf stat -e '{cycles,instructions}' kill (test-stat-group1)
|
| D | test-stat-group1 | 3 args = -e '{cycles,instructions}' kill >/dev/null 2>&1
|
| /Linux-v5.4/arch/nios2/platform/ |
| D | Kconfig.platform | 52 comment "Nios II instructions"
81 bool "Enable BMX instructions"
85 the BMX Bit Manipulation Extension instructions. Enables
89 bool "Enable CDX instructions"
93 the CDX Bit Manipulation Extension instructions. Enables
|
| /Linux-v5.4/drivers/media/pci/tw68/ |
| D | tw68-risc.c | 137 u32 instructions, fields; in tw68_risc_buffer() local
151 instructions = fields * (1 + (((bpl + padding) * lines) / in tw68_risc_buffer()
153 buf->size = instructions * 8; in tw68_risc_buffer()
|
| /Linux-v5.4/arch/m68k/ifpsp060/ |
| D | fplsp.doc | 36 FP instructions not implemented in 68060 hardware. These
37 instructions normally take exception vector #11
40 By re-compiling a program that uses these instructions, and
42 instructions, a program can avoid the overhead associated
110 this exception using implemented floating-point instructions.
120 The package does not attempt to correctly emulate instructions
126 subroutine calls for all fp instructions. The code does NOT emulate
|
| /Linux-v5.4/Documentation/arm/nwfpe/ |
| D | netwinder-fpe.rst | 9 instructions. It follows the conventions in the ARM manual.
28 These instructions are fully implemented.
40 These instructions are fully implemented. They store/load three words
49 Conversions, read/write status/control register instructions
62 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
66 Compare instructions
95 equivalent to the MUF/DVF/RDV instructions. This is acceptable according
|
| /Linux-v5.4/drivers/acpi/apei/ |
| D | apei-internal.h | 33 u32 instructions; member
40 u32 instructions,
|
| /Linux-v5.4/drivers/media/pci/cx88/ |
| D | cx88-core.c | 135 u32 instructions, fields; in cx88_risc_buffer() local
150 instructions = fields * (1 + ((bpl + padding) * lines) / in cx88_risc_buffer()
152 instructions += 4; in cx88_risc_buffer()
153 risc->size = instructions * 8; in cx88_risc_buffer()
180 u32 instructions; in cx88_risc_databuffer() local
189 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; in cx88_risc_databuffer()
190 instructions += 3; in cx88_risc_databuffer()
191 risc->size = instructions * 8; in cx88_risc_databuffer()
|
| /Linux-v5.4/arch/ia64/ |
| D | Kconfig.debug | 45 compare-and-exchange instructions. This is slow! Itaniums
54 and restore instructions. It's useful for tracking down spinlock
|
| /Linux-v5.4/Documentation/core-api/ |
| D | refcount-vs-atomic.rst | 36 each ``atomic_*()`` and ``refcount_*()`` operation is atomic and instructions
42 stores (all po-earlier instructions) on the same CPU are completed
50 stores (all po-earlier instructions) on the same CPU are completed
58 stores (all po-later instructions) on the same CPU are
|
