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Searched refs:i915_ggtt_offset (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_coherency.c214 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
215 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
220 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
224 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_gt.h50 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
Dintel_timeline.c325 i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_pin()
462 tl->hwsp_offset += i915_ggtt_offset(vma); in __intel_timeline_get_seqno()
517 *hwsp = i915_ggtt_offset(cl->hwsp->vma) + in intel_timeline_read_hwsp()
Dintel_renderstate.c118 so->batch_offset = i915_ggtt_offset(so->vma); in render_state_setup()
Dintel_engine_cs.c1293 i915_ggtt_offset(rq->ring->vma), in intel_engine_print_registers()
1305 i915_ggtt_offset(rq->ring->vma), in intel_engine_print_registers()
1389 i915_ggtt_offset(rq->ring->vma)); in intel_engine_dump()
1536 return ring == i915_ggtt_offset(rq->ring->vma); in match_ring()
Dselftest_lrc.c98 *cs++ = i915_ggtt_offset(vma) + 4 * idx; in emit_semaphore_chain()
103 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in emit_semaphore_chain()
166 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in release_queue()
395 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
406 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
439 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
Dintel_ringbuffer.c595 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
689 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
716 i915_ggtt_offset(ring->vma)); in xcs_resume()
1646 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
1653 *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; in mi_set_context()
Dintel_lrc.c246 return (i915_ggtt_offset(engine->status_page.vma) + in intel_hws_preempt_address()
447 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; in lrc_descriptor()
1770 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma); in __execlists_update_reg_state()
2327 i915_ggtt_offset(engine->status_page.vma)); in enable_execlists()
3226 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in execlists_init_reg_state()
3238 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in execlists_init_reg_state()
Dintel_workarounds.c1492 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; in wa_list_srm()
Dselftest_workarounds.c136 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; in read_nonprivs()
/Linux-v5.4/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.h128 u32 offset = i915_ggtt_offset(vma); in intel_guc_ggtt_offset()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_perf.c527 u32 gtt_offset = i915_ggtt_offset(vma); in oa_buffer_check_unlocked()
661 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_append_oa_reports()
949 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_append_oa_reports()
1264 stream->specific_ctx_id = i915_ggtt_offset(ce->state); in oa_get_render_ctx_id()
1396 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_init_oa_buffer()
1446 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_init_oa_buffer()
1545 i915_ggtt_offset(stream->oa_buffer.vma), in alloc_oa_buffer()
1728 offset = i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; in gen8_store_flex()
Di915_vma.h214 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
Di915_gem.c353 node.start = i915_ggtt_offset(vma); in i915_gem_gtt_pread()
563 node.start = i915_ggtt_offset(vma); in i915_gem_gtt_pwrite_fast()
1039 i915_ggtt_offset(vma), alignment, in i915_gem_object_pin()
Di915_gpu_error.c1179 erq->start = i915_ggtt_offset(request->ring->vma); in record_request()
Di915_gem_gtt.c1820 u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE; in pd_vma_bind()
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_overlay.c800 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
817 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image()
819 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image()
1325 overlay->flip_addr = i915_ggtt_offset(vma); in get_registers()
Dintel_fbdev.c265 i915_ggtt_offset(vma)); in intelfb_create()
Dintel_display_types.h1523 return i915_ggtt_offset(state->vma); in intel_plane_ggtt_offset()
Dintel_fbc.c257 i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID); in ilk_fbc_activate()
/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dscheduler.c494 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); in prepare_shadow_batch_buffer()
562 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); in prepare_shadow_wa_ctx()
/Linux-v5.4/drivers/gpu/drm/i915/gem/
Di915_gem_context.c1118 offset = i915_ggtt_offset(ce->state) + in gen8_emit_rpcs_config()