Searched refs:divided_rate (Results 1 – 2 of 2) sorted by relevance
363 u32 rate, divided_rate = 0; in tcb_clksrc_init() local431 divided_rate = tmp; in tcb_clksrc_init()437 pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000, in tcb_clksrc_init()438 ((divided_rate % 1000000) + 500) / 1000); in tcb_clksrc_init()465 ret = clocksource_register_hz(&clksrc, divided_rate); in tcb_clksrc_init()474 sched_clock_register(tc_sched_clock, 32, divided_rate); in tcb_clksrc_init()476 tc_delay_timer.freq = divided_rate; in tcb_clksrc_init()
124 unsigned long divided_rate, divided_rate_down, best_rate; in calc_best_divided_rate() local135 divided_rate = parent_rate / div; in calc_best_divided_rate()137 if (abs(rate - divided_rate_down) < abs(rate - divided_rate)) in calc_best_divided_rate()140 best_rate = divided_rate; in calc_best_divided_rate()
