| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | hardwaremanager.c | 288 const struct amd_pp_display_configuration *display_config) in phm_store_dal_configuration_data() argument
295 if (display_config == NULL) in phm_store_dal_configuration_data()
299 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); in phm_store_dal_configuration_data()
301 for (index = 0; index < display_config->num_path_including_non_display; index++) { in phm_store_dal_configuration_data()
302 if (display_config->displays[index].controller_id != 0) in phm_store_dal_configuration_data()
316 display_config->cpu_pstate_separation_time, in phm_store_dal_configuration_data()
317 display_config->cpu_cc6_disable, in phm_store_dal_configuration_data()
318 display_config->cpu_pstate_disable, in phm_store_dal_configuration_data()
319 display_config->nb_pstate_switch_disable); in phm_store_dal_configuration_data()
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| D | vega12_hwmgr.c | 1479 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()
1480 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()
1481 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()
1486 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1487 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1488 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
2179 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()
2180 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()
2182 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()
2233 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega12_apply_clocks_adjust_rules()
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| D | vega20_hwmgr.c | 2300 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2301 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2302 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
3564 hwmgr->display_config->num_display); in vega20_display_configuration_changed_task()
3638 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
3639 !hwmgr->display_config->multi_monitor_in_sync) || in vega20_apply_clocks_adjust_rules()
3641 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
3692 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
3693 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
3700 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()
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| D | smu10_hwmgr.c | 198 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()
571 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; in smu10_dpm_force_dpm_level()
572 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
664 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
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| D | smu7_hwmgr.c | 2924 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
2925 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()
2956 if (hwmgr->display_config->num_display == 0) in smu7_apply_state_adjust_rules()
2959 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in smu7_apply_state_adjust_rules()
2960 !hwmgr->display_config->multi_monitor_in_sync) || in smu7_apply_state_adjust_rules()
2962 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time); in smu7_apply_state_adjust_rules()
3640 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()
4048 if (hwmgr->display_config->num_display > 1 && in smu7_notify_smc_display_config_after_ps_adjustment()
4049 !hwmgr->display_config->multi_monitor_in_sync) in smu7_notify_smc_display_config_after_ps_adjustment()
4070 …display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->nu… in smu7_program_display_gap()
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| D | vega10_hwmgr.c | 3179 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3180 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()
3220 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()
3223 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega10_apply_state_adjust_rules()
3224 !hwmgr->display_config->multi_monitor_in_sync) || in vega10_apply_state_adjust_rules()
3256 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()
3322 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in vega10_find_dpm_states_clocks_in_dpm_table()
3924 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()
3925 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()
3926 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment()
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| D | smu8_hwmgr.c | 700 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()
755 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()
1053 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()
1054 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()
1062 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
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| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/ |
| D | amdgpu_smu.c | 868 smu->display_config = &adev->pm.pm_display_cfg; in smu_sw_init()
1399 const struct amd_pp_display_configuration *display_config) in smu_display_configuration_change() argument
1407 if (!display_config) in smu_display_configuration_change()
1413 display_config->min_dcef_deep_sleep_set_clk / 100); in smu_display_configuration_change()
1415 for (index = 0; index < display_config->num_path_including_non_display; index++) { in smu_display_configuration_change()
1416 if (display_config->displays[index].controller_id != 0) in smu_display_configuration_change()
1422 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time, in smu_display_configuration_change()
1423 display_config->cpu_cc6_disable, in smu_display_configuration_change()
1424 display_config->cpu_pstate_disable, in smu_display_configuration_change()
1425 display_config->nb_pstate_switch_disable); in smu_display_configuration_change()
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| D | vega20_ppt.c | 2094 smu->display_config->num_display); in vega20_display_config_changed()
2109 disable_mclk_switching = ((1 < smu->display_config->num_display) && in vega20_apply_clocks_adjust_rules()
2110 !smu->display_config->multi_monitor_in_sync) || vblank_too_short; in vega20_apply_clocks_adjust_rules()
2111 latency = smu->display_config->dce_tolerable_mclk_in_active_latency; in vega20_apply_clocks_adjust_rules()
2158 if (dpm_table->dpm_state.hard_min_level < (smu->display_config->min_mem_set_clock / 100)) in vega20_apply_clocks_adjust_rules()
2159 dpm_table->dpm_state.hard_min_level = smu->display_config->min_mem_set_clock / 100; in vega20_apply_clocks_adjust_rules()
2166 if (dpm_table->dpm_levels[i].value >= (smu->display_config->min_mem_set_clock / 100)) { in vega20_apply_clocks_adjust_rules()
2174 if (smu->display_config->nb_pstate_switch_disable) in vega20_apply_clocks_adjust_rules()
2256 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in vega20_notify_smc_dispaly_config()
2257 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_dispaly_config()
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| D | navi10_ppt.c | 879 smu->display_config->num_display); in navi10_display_config_changed()
1256 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_dispaly_config()
1257 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_dispaly_config()
1258 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_dispaly_config()
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| D | amd_powerplay.c | 57 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()
1036 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change() argument
1044 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
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| /Linux-v5.4/arch/arm/mach-davinci/include/mach/ |
| D | da8xx.h | 124 (struct vpif_display_config *display_config);
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| /Linux-v5.4/arch/arm/mach-davinci/ |
| D | dm646x.c | 609 void dm646x_setup_vpif(struct vpif_display_config *display_config, in dm646x_setup_vpif() argument
627 vpif_display_dev.dev.platform_data = display_config; in dm646x_setup_vpif()
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| D | da850.c | 584 *display_config) in da850_register_vpif_display()
586 da850_vpif_display_dev.dev.platform_data = display_config; in da850_register_vpif_display()
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| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/inc/ |
| D | hardwaremanager.h | 431 const struct amd_pp_display_configuration *display_config);
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| D | amdgpu_smu.h | 354 struct amd_pp_display_configuration *display_config; member
806 *display_config);
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| D | hwmgr.h | 783 const struct amd_pp_display_configuration *display_config; member
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| /Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | vegam_smumgr.c | 836 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()
840 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()
1010 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()
1011 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in vegam_populate_single_memory_level()
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| D | fiji_smumgr.c | 978 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()
982 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()
1203 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in fiji_populate_single_memory_level()
1204 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in fiji_populate_single_memory_level()
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| D | polaris10_smumgr.c | 944 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in polaris10_populate_single_graphic_level()
948 hwmgr->display_config->min_core_set_clock_in_sr); in polaris10_populate_single_graphic_level()
1106 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in polaris10_populate_single_memory_level()
1107 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in polaris10_populate_single_memory_level()
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| D | iceland_smumgr.c | 932 hwmgr->display_config->min_core_set_clock_in_sr; in iceland_populate_single_graphic_level()
1282 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in iceland_populate_single_memory_level()
1283 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in iceland_populate_single_memory_level()
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| D | tonga_smumgr.c | 659 hwmgr->display_config->min_core_set_clock_in_sr; in tonga_populate_single_graphic_level()
1016 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in tonga_populate_single_memory_level()
1017 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in tonga_populate_single_memory_level()
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| D | ci_smumgr.c | 1234 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()
1235 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; in ci_populate_single_memory_level()
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