| /Linux-v5.4/drivers/mmc/host/ |
| D | dw_mmc-exynos.c | 133 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
137 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
139 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
141 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
145 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
147 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
156 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
203 u32 clksel; in dw_mci_exynos_resume_noirq() local
212 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_resume_noirq()
214 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_resume_noirq()
[all …]
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| D | dw_mmc-zx.c | 38 unsigned int clksel; in dw_mci_zx_emmc_set_delay() local
54 ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel); in dw_mci_zx_emmc_set_delay()
59 clksel &= ~CLK_SAMP_DELAY_MASK; in dw_mci_zx_emmc_set_delay()
60 clksel |= CLK_SAMP_DELAY(delay); in dw_mci_zx_emmc_set_delay()
62 clksel &= ~READ_DQS_DELAY_MASK; in dw_mci_zx_emmc_set_delay()
63 clksel |= READ_DQS_DELAY(delay); in dw_mci_zx_emmc_set_delay()
66 regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel); in dw_mci_zx_emmc_set_delay()
74 ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel); in dw_mci_zx_emmc_set_delay()
78 } while (--loop && !(clksel & ZX_DLL_LOCKED)); in dw_mci_zx_emmc_set_delay()
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| /Linux-v5.4/drivers/clocksource/ |
| D | timer-cadence-ttc.c | 479 int clksel, ret; in ttc_timer_init() local
506 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
507 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_init()
508 clk_cs = of_clk_get(timer, clksel); in ttc_timer_init()
514 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
515 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_init()
516 clk_ce = of_clk_get(timer, clksel); in ttc_timer_init()
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| /Linux-v5.4/drivers/clk/rockchip/ |
| D | clk-cpu.c | 109 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
111 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
115 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
116 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
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| /Linux-v5.4/arch/mips/ralink/ |
| D | rt3883.c | 67 u32 clksel; in ralink_clk_init() local
71 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) & in ralink_clk_init()
75 switch (clksel) { in ralink_clk_init()
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| /Linux-v5.4/drivers/clk/ |
| D | clk-qoriq.c | 57 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
789 u32 clksel; in mux_set_parent() local
794 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
795 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
803 u32 clksel; in mux_get_parent() local
806 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
808 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
836 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
839 pll = hwc->info->clksel[idx].pll; in get_pll_div()
840 div = hwc->info->clksel[idx].div; in get_pll_div()
[all …]
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| /Linux-v5.4/arch/arm/mach-imx/ |
| D | mach-imx6q.c | 183 u32 clksel; in imx6q_1588_init() local
208 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
215 clksel); in imx6q_1588_init()
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| /Linux-v5.4/drivers/gpu/drm/zte/ |
| D | zx_vou.c | 138 u32 clksel; member
145 .clksel = VOU_CLK_GL0_SEL,
149 .clksel = VOU_CLK_GL1_SEL,
157 .clksel = VOU_CLK_VL0_SEL,
161 .clksel = VOU_CLK_VL1_SEL,
165 .clksel = VOU_CLK_VL2_SEL,
618 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0); in zx_vou_layer_enable()
622 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, in zx_vou_layer_enable()
623 bits->clksel); in zx_vou_layer_enable()
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| /Linux-v5.4/drivers/gpu/drm/rcar-du/ |
| D | rcar_lvds.c | 186 u32 clksel; member
191 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc() argument
299 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
333 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in __rcar_lvds_pll_setup_d3_e3()
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| /Linux-v5.4/drivers/mfd/ |
| D | asic3.c | 387 unsigned long clksel = 0; in asic3_irq_probe() local
397 clksel |= CLOCK_SEL_CX; in asic3_irq_probe()
399 clksel); in asic3_irq_probe()
957 unsigned long clksel; in asic3_probe() local
986 clksel = 0; in asic3_probe()
987 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel); in asic3_probe()
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