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Searched refs:WREG32_RLC (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v9.c141 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
142 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
285 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); in kgd_gfx_v9_hqd_load()
294 WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); in kgd_gfx_v9_hqd_load()
300 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); in kgd_gfx_v9_hqd_load()
329 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_hqd_load()
331 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_hqd_load()
333 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_gfx_v9_hqd_load()
335 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_gfx_v9_hqd_load()
342 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), in kgd_gfx_v9_hqd_load()
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Dsoc15_common.h73 #define WREG32_RLC(reg, value) \ macro
118 WREG32_RLC(target_reg, value); \
122 WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
127 WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
Dsoc15.c434 WREG32_RLC(reg, tmp); in soc15_program_register_sequence()
Dgfx_v9_0.c2605 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), in gfx_v9_0_init_csb()
2607 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), in gfx_v9_0_init_csb()
2609 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), in gfx_v9_0_init_csb()