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Searched refs:RREG32_NO_KIQ (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c323 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
328 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
337 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
345 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
356 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
372 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
377 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()
393 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
403 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
502 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq()
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Dmxgpu_ai.c56 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
66 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
138 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
186 val = RREG32_NO_KIQ( in xgpu_ai_get_pp_clk()
256 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
303 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
356 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
Dvega10_ih.c394 wptr = RREG32_NO_KIQ(reg); in vega10_ih_get_wptr()
419 tmp = RREG32_NO_KIQ(reg); in vega10_ih_get_wptr()
494 v = RREG32_NO_KIQ(reg_rptr); in vega10_ih_irq_rearm()
Dnavi10_ih.c221 wptr = RREG32_NO_KIQ(reg); in navi10_ih_get_wptr()
237 tmp = RREG32_NO_KIQ(reg); in navi10_ih_get_wptr()
Dvi.c92 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_rreg()
93 r = RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_rreg()
104 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_wreg()
106 (void)RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_wreg()
117 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
Dgmc_v10_0.c245 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); in gmc_v10_0_flush_vm_hub()
249 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); in gmc_v10_0_flush_vm_hub()
Damdgpu_virt.c35 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
Damdgpu_discovery.c146 *p++ = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_discovery_read_binary()
Dgmc_v9_0.c501 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); in gmc_v9_0_flush_gpu_tlb()
504 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); in gmc_v9_0_flush_gpu_tlb()
Damdgpu_ttm.c1567 value = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_ttm_access_memory()
2218 value = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_ttm_vram_read()
Damdgpu.h1057 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro