Searched refs:REGBASE (Results 1 – 7 of 7) sorted by relevance
16 #define REGBASE 0x10000000 macro18 #define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)19 #define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)20 #define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)21 #define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)22 #define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)23 #define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)24 #define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)25 #define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)26 #define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)[all …]
88 REGBASE = DPRBASE + 0x1000 define89 PICR = REGBASE + 0x026 // 16-bit periodic irq control90 PITR = REGBASE + 0x02A // 16-bit periodic irq timing91 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options92 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config93 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask94 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service95 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap96 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap97 PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap[all …]
11 #define IC_GROUP0_PEND (REGBASE + 0x38000)12 #define IC_GROUP0_MASK (REGBASE + 0x38008)
12 #define REGBASE 0x18000000 macro13 #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
48 .start = REGBASE + GPIOBASE,49 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
44 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
222 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
