Searched refs:RADEON_SCLK_CNTL (Results 1 – 2 of 2) sorted by relevance
57 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()403 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()405 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()447 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()464 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()481 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()495 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()499 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()518 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()555 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()[all …]
1663 #define RADEON_SCLK_CNTL 0x000d /* PLL */ macro
