Searched refs:QE_PIO_PINS (Results 1 – 3 of 3) sorted by relevance
57 pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); in __par_io_config_pin()67 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()72 pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - in __par_io_config_pin()73 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()76 new_mask2bits = (u32) (dir << (QE_PIO_PINS - in __par_io_config_pin()77 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()80 if (pin > (QE_PIO_PINS / 2) - 1) { in __par_io_config_pin()92 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? in __par_io_config_pin()96 new_mask2bits = (u32) (assignment << (QE_PIO_PINS - in __par_io_config_pin()97 (pin % (QE_PIO_PINS / 2) + 1) * 2)); in __par_io_config_pin()[all …]
28 unsigned long pin_flags[QE_PIO_PINS];57 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_get()68 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_set()98 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); in qe_gpio_set_multiple()100 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); in qe_gpio_set_multiple()250 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated()251 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated()252 bool second_reg = pin > (QE_PIO_PINS / 2) - 1; in qe_pin_set_dedicated()321 gc->ngpio = QE_PIO_PINS; in qe_add_gpiochips()
142 #define QE_PIO_PINS 32 macro
