Searched refs:PRCMU_DSI0CLK (Results 1 – 5 of 5) sorted by relevance
68 #define PRCMU_DSI0CLK 47 macro
220 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); in u8500_clk_init()221 prcmu_clk[PRCMU_DSI0CLK] = clk; in u8500_clk_init()
1456 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in db8500_prcmu_request_clock()1457 return request_dsiclk((clock - PRCMU_DSI0CLK), enable); in db8500_prcmu_request_clock()1632 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_clock_rate()1633 return dsiclk_rate(clock - PRCMU_DSI0CLK); in prcmu_clock_rate()1815 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_round_clock_rate()1987 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_set_clock_rate()1988 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); in prcmu_set_clock_rate()
72 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1070 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
