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Searched refs:PIPE0_DMIF_BUFFER_CONTROL (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.h183 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
184 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
/Linux-v5.4/drivers/gpu/drm/radeon/
Dsid.h328 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
Dcikd.h440 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
Devergreend.h1216 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
Devergreen.c1870 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
1873 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
Dsi.c2007 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
2010 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
Dcik.c8858 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
8861 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dsid.h330 #define PIPE0_DMIF_BUFFER_CONTROL 0x0328 macro
Ddce_v10_0.c627 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v10_0_line_buffer_adjust()
632 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v10_0_line_buffer_adjust()
Ddce_v11_0.c653 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v11_0_line_buffer_adjust()
658 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v11_0_line_buffer_adjust()