Searched refs:HALT (Results 1 – 9 of 9) sorted by relevance
| /Linux-v5.4/arch/arm/mach-clps711x/ |
| D | board-dt.c | 22 # define HALT (0x0800) macro
42 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
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| /Linux-v5.4/arch/mips/dec/ |
| D | int-handler.S | 236 FEXPORT(cpu_all_int) # HALT, timers, software junk
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| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 395 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_enable()
397 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v2_4_enable()
972 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_soft_reset()
979 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_soft_reset()
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| D | sdma_v3_0.c | 630 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_enable()
632 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v3_0_enable()
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| D | sdma_v5_0.c | 589 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_0_enable()
719 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v5_0_gfx_resume()
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| D | sdma_v4_0.c | 952 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_0_enable()
1324 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v4_0_start()
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| /Linux-v5.4/Documentation/s390/ |
| D | vfio-ccw.rst | 232 Currently, CLEAR SUBCHANNEL and HALT SUBCHANNEL use this region.
336 START SUBCHANNEL, and to issue HALT SUBCHANNEL and CLEAR SUBCHANNEL.
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| D | cds.rst | 164 ccw_device_halt() function. Some devices require to initially issue a HALT
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| /Linux-v5.4/arch/arc/kernel/ |
| D | entry-compact.S | 373 ; If this does happen we simply HALT as it means a BUG !!!
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