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Searched refs:FDI_RX_CTL (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_ddi.c1093 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1094 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1099 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1133 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1134 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
1164 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1165 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
3444 val = I915_READ(FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable()
3446 I915_WRITE(FDI_RX_CTL(PIPE_A), val); in intel_ddi_fdi_post_disable()
3456 val = I915_READ(FDI_RX_CTL(PIPE_A)); in intel_ddi_fdi_post_disable()
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Dintel_display.c1146 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
1178 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx_pll()
4456 reg = FDI_RX_CTL(pipe); in intel_fdi_normal_train()
4509 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
4544 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
4614 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
4667 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
4744 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
4765 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
4800 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
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Dintel_crt.c1069 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dhandlers.c588 fdi_rx_ctl = FDI_RX_CTL(pipe); in check_fdi_rx_train_status()
635 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
2220 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2221 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2222 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_reg.h8401 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) macro