Searched refs:EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (Results 1 – 1 of 1) sorted by relevance
61 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0) macro144 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ; in exynos4x12_rate_to_clk()