Searched refs:DMC (Results 1 – 12 of 12) sorted by relevance
6 PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC).8 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.12 The DMC and L3C support up to 4 counters. Counters are independently19 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
19 #define DMC 0x600000UL macro1978 #define RXDMA_CFIG1(IDX) (DMC + 0x00000UL + (IDX) * 0x200UL)1984 #define RXDMA_CFIG2(IDX) (DMC + 0x00008UL + (IDX) * 0x200UL)1990 #define RBR_CFIG_A(IDX) (DMC + 0x00010UL + (IDX) * 0x200UL)1996 #define RBR_CFIG_B(IDX) (DMC + 0x00018UL + (IDX) * 0x200UL)2026 #define RBR_KICK(IDX) (DMC + 0x00020UL + (IDX) * 0x200UL)2029 #define RBR_STAT(IDX) (DMC + 0x00028UL + (IDX) * 0x200UL)2032 #define RBR_HDH(IDX) (DMC + 0x00030UL + (IDX) * 0x200UL)2035 #define RBR_HDL(IDX) (DMC + 0x00038UL + (IDX) * 0x200UL)2038 #define RCRCFIG_A(IDX) (DMC + 0x00040UL + (IDX) * 0x200UL)[all …]
58 VDD_MIF |--- DMC73 VDD_INT |--- DMC (parent device)90 VDD_MIF |--- DMC146 : VDD_MIF |--- DMC (Dynamic Memory Controller)190 The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
1 * Rockchip rk3399 DMC (Dynamic Memory Controller) device13 - center-supply: DMC supply node.
39 21: DMC
16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
207 CSR firmware support for DMC
119 tristate "ARM RK3399 DMC DEVFREQ Driver"126 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
8 usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
115 in the DDR4 Memory Controller (DMC).
20 binary to perform a malicious action when executed [DMC-CBC-ATTACK]. Since436 [DMC-CBC-ATTACK] http://www.jakoblell.com/blog/2013/12/22/practical-malleability-attack-against…
885 - DMC TSC-10/25964 bool "DMC TSC-10/25 device support" if EXPERT
