Searched refs:DCLK (Results 1 – 13 of 13) sorted by relevance
144 uint32_t DCLK; member
99 58: 3DCLK
220 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
761 ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK); in init_non_clock_fields()764 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
792 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
3164 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()3257 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()3405 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
1387 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
3052 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()3119 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
129 CLK_MAP(DCLK, PPCLK_DCLK),
133 CLK_MAP(DCLK, PPCLK_DCLK),
151 CLK_MAP(DCLK, PPCLK_DCLK),
7503 min_ring_freq = I915_READ(DCLK) & 0xf; in gen6_update_ring_freq()
3595 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro
