Home
last modified time | relevance | path

Searched refs:CGU_CLK_DIV (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/drivers/clk/ingenic/
Djz4740-cgu.c91 "pll half", CGU_CLK_DIV,
100 "cclk", CGU_CLK_DIV,
109 "hclk", CGU_CLK_DIV,
118 "pclk", CGU_CLK_DIV,
127 "mclk", CGU_CLK_DIV,
136 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
146 "lcd_pclk", CGU_CLK_DIV,
152 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
160 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
168 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
Djz4770-cgu.c146 "cclk", CGU_CLK_DIV,
154 "h0clk", CGU_CLK_DIV,
162 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
171 "h2clk", CGU_CLK_DIV,
179 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
188 "pclk", CGU_CLK_DIV,
199 "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
206 "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
213 "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
220 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
[all …]
Djz4725b-cgu.c76 "pll half", CGU_CLK_DIV,
85 "cclk", CGU_CLK_DIV,
94 "hclk", CGU_CLK_DIV,
103 "pclk", CGU_CLK_DIV,
112 "mclk", CGU_CLK_DIV,
121 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
131 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
138 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
146 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
154 "mmc_mux", CGU_CLK_DIV,
[all …]
Djz4780-cgu.c290 "cpu", CGU_CLK_DIV,
296 "l2cache", CGU_CLK_DIV,
302 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
317 "ahb2", CGU_CLK_DIV,
323 "pclk", CGU_CLK_DIV,
329 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
336 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
345 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
358 "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
366 "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
[all …]
Dcgu.c374 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
448 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
471 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
709 if (caps & CGU_CLK_DIV) { in ingenic_register_clock()
710 caps &= ~CGU_CLK_DIV; in ingenic_register_clock()
Dcgu.h151 CGU_CLK_DIV = BIT(5), enumerator