Searched refs:writer_wm_sets (Results 1 – 11 of 11) sorted by relevance
524 if (ranges->writer_wm_sets[i].wm_inst > 3) in pp_rv_set_wm_ranges()528 ranges->writer_wm_sets[i].wm_inst; in pp_rv_set_wm_ranges()530 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()532 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()534 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()536 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
1579 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()1580 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()1581 ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; in dcn_bw_notify_pplib_of_wm_ranges()1582 ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()1583 ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; in dcn_bw_notify_pplib_of_wm_ranges()1591 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()1592 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200; in dcn_bw_notify_pplib_of_wm_ranges()1593 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()1594 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800; in dcn_bw_notify_pplib_of_wm_ranges()1595 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()[all …]
508 ranges->writer_wm_sets[0].wm_inst = WM_A; in build_watermark_ranges()509 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in build_watermark_ranges()510 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in build_watermark_ranges()511 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in build_watermark_ranges()512 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in build_watermark_ranges()
517 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in yellow_carp_set_watermarks_table()519 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in yellow_carp_set_watermarks_table()521 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in yellow_carp_set_watermarks_table()523 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in yellow_carp_set_watermarks_table()526 clock_ranges->writer_wm_sets[i].wm_inst; in yellow_carp_set_watermarks_table()
1064 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()1066 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in renoir_set_watermarks_table()1068 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in renoir_set_watermarks_table()1070 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in renoir_set_watermarks_table()1073 clock_ranges->writer_wm_sets[i].wm_inst; in renoir_set_watermarks_table()1075 clock_ranges->writer_wm_sets[i].wm_type; in renoir_set_watermarks_table()
93 struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS]; member
1561 ranges.writer_wm_sets[0].wm_inst = 0; in set_wm_ranges()1562 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()1563 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()1564 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()1565 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1620 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in vangogh_set_watermarks_table()1622 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in vangogh_set_watermarks_table()1624 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in vangogh_set_watermarks_table()1626 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in vangogh_set_watermarks_table()1629 clock_ranges->writer_wm_sets[i].wm_inst; in vangogh_set_watermarks_table()
1956 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()1958 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in navi10_set_watermarks_table()1960 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in navi10_set_watermarks_table()1962 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in navi10_set_watermarks_table()1965 clock_ranges->writer_wm_sets[i].wm_inst; in navi10_set_watermarks_table()
1638 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()1640 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()1642 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()1644 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()1647 clock_ranges->writer_wm_sets[i].wm_inst; in sienna_cichlid_set_watermarks_table()
3896 ranges.writer_wm_sets[0].wm_inst = 0; in dcn20_resource_construct()3897 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()3898 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()3899 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()3900 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
