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Searched refs:sdma_rlc_reg_offset (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_arcturus.c75 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
117 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
121 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
123 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
131 uint32_t sdma_rlc_reg_offset; in kgd_arcturus_hqd_sdma_load() local
138 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_arcturus_hqd_sdma_load()
141 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_arcturus_hqd_sdma_load()
146 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_arcturus_hqd_sdma_load()
156 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_arcturus_hqd_sdma_load()
161 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_arcturus_hqd_sdma_load()
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Damdgpu_amdkfd_gfx_v9.c199 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
217 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
221 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
223 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
406 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
413 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_hqd_sdma_load()
416 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
421 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
431 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_hqd_sdma_load()
436 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
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Damdgpu_amdkfd_gfx_v10.c394 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
401 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_hqd_sdma_load()
404 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
409 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
419 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_hqd_sdma_load()
424 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
425 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
427 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, in kgd_hqd_sdma_load()
430 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); in kgd_hqd_sdma_load()
432 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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Damdgpu_amdkfd_gfx_v10_3.c146 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
172 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
176 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
178 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
379 uint32_t sdma_rlc_reg_offset; in hqd_sdma_load_v10_3() local
386 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in hqd_sdma_load_v10_3()
389 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in hqd_sdma_load_v10_3()
394 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in hqd_sdma_load_v10_3()
404 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in hqd_sdma_load_v10_3()
409 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in hqd_sdma_load_v10_3()
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Damdgpu_amdkfd_gfx_v8.c285 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
289 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load()
290 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
295 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
307 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
308 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
312 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
314 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
317 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, in kgd_hqd_sdma_load()
319 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_hqd_sdma_load()
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Damdgpu_amdkfd_gfx_v7.c298 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
302 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load()
304 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
309 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
321 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
322 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
326 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
328 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
331 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, in kgd_hqd_sdma_load()
333 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); in kgd_hqd_sdma_load()
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