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Searched refs:rb_cntl (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/radeon/
Dni_dma.c158 u32 rb_cntl; in cayman_dma_stop() local
165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
166 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
171 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
189 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
212 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in cayman_dma_resume()
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Dr600_dma.c100 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local
105 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop()
106 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
122 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
133 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume()
135 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
148 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume()
169 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
Dcik_sdma.c251 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
264 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop()
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
367 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
390 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume()
392 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
405 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume()
414 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); in cik_sdma_gfx_resume()
Dni.c1676 uint32_t rb_cntl; in cayman_cp_resume() local
1681 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1682 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume()
1684 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume()
1686 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dsdma_v2_4.c347 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local
355 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
356 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
357 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
415 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local
441 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
442 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
444 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume()
445 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v2_4_gfx_resume()
448 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_resume()
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Dsdma_v4_0.c990 u32 rb_cntl, ib_cntl; in sdma_v4_0_gfx_stop() local
1001 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); in sdma_v4_0_gfx_stop()
1002 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_0_gfx_stop()
1003 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); in sdma_v4_0_gfx_stop()
1032 u32 rb_cntl, ib_cntl; in sdma_v4_0_page_stop() local
1045 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); in sdma_v4_0_page_stop()
1046 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, in sdma_v4_0_page_stop()
1048 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); in sdma_v4_0_page_stop()
1148 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) in sdma_v4_0_rb_cntl() argument
1153 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_rb_cntl()
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Dsdma_v3_0.c521 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local
529 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
530 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
531 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
650 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v3_0_gfx_resume() local
679 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
682 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v3_0_gfx_resume()
683 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v3_0_gfx_resume()
686 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_resume()
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Dsi_dma.c117 u32 rb_cntl; in si_dma_stop() local
123 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
124 rb_cntl &= ~DMA_RB_ENABLE; in si_dma_stop()
125 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
135 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
147 rb_cntl = rb_bufsz << 1; in si_dma_start()
149 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in si_dma_start()
151 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
162 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in si_dma_start()
179 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()
Dsdma_v5_2.c478 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_stop() local
488 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_stop()
489 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_2_gfx_stop()
490 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_stop()
599 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_resume() local
617 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume()
618 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_2_gfx_resume()
620 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_2_gfx_resume()
621 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_2_gfx_resume()
624 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_resume()
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Dsdma_v5_0.c591 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local
599 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop()
600 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop()
601 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop()
717 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume() local
736 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume()
737 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume()
739 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_0_gfx_resume()
740 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_0_gfx_resume()
743 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_resume()
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Dcik_sdma.c314 u32 rb_cntl; in cik_sdma_gfx_stop() local
322 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
323 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; in cik_sdma_gfx_stop()
324 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
437 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
465 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
467 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | in cik_sdma_gfx_resume()
470 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_resume()
484 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; in cik_sdma_gfx_resume()
494 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); in cik_sdma_gfx_resume()