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Searched refs:rb_bufsz (Results 1 – 25 of 39) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/radeon/
Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
Dr600_dma.c123 u32 rb_bufsz; in r600_dma_resume() local
130 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
Dni_dma.c190 u32 rb_bufsz; in cayman_dma_resume() local
209 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
Dcik_sdma.c368 u32 rb_bufsz; in cik_sdma_gfx_resume() local
387 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dr600.c2720 u32 rb_bufsz; in r600_cp_resume() local
2730 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2731 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2782 u32 rb_bufsz; in r600_ring_init() local
2786 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2787 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3468 u32 rb_bufsz; in r600_ih_ring_init() local
3471 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3472 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3674 int rb_bufsz; in r600_irq_init() local
[all …]
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c44 u32 rb_bufsz; in amdgpu_ih_ring_init() local
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
Dsi_ih.c65 int rb_bufsz; in si_ih_irq_init() local
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
81 (rb_bufsz << 1) | in si_ih_irq_init()
Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
Duvd_v3_1.c323 uint32_t rb_bufsz; in uvd_v3_1_start() local
433 rb_bufsz = order_base_2(ring->ring_size); in uvd_v3_1_start()
434 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v3_1_start()
435 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
Duvd_v4_2.c279 uint32_t rb_bufsz; in uvd_v4_2_start() local
389 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
390 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
391 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
Dtonga_ih.c106 int rb_bufsz; in tonga_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
Duvd_v5_0.c316 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
413 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
415 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
Dvcn_v2_5.c770 uint32_t rb_bufsz, tmp; in vcn_v2_5_start_dpg_mode() local
866 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
867 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
913 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
1058 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1059 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1162 uint32_t offset, size, tmp, i, rb_bufsz; in vcn_v2_5_sriov_start() local
1277 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1278 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
Dsi_dma.c135 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
146 rb_bufsz = order_base_2(ring->ring_size / 4); in si_dma_start()
147 rb_cntl = rb_bufsz << 1; in si_dma_start()
Dvcn_v1_0.c781 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_spg_mode() local
900 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_spg_mode()
901 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_spg_mode()
955 uint32_t rb_bufsz, tmp; in vcn_v1_0_start_dpg_mode() local
1058 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_dpg_mode()
1059 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start_dpg_mode()
Dvega10_ih.c160 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl() local
168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_rb_cntl()
Dvcn_v2_0.c792 uint32_t rb_bufsz, tmp; in vcn_v2_0_start_dpg_mode() local
882 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
883 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
929 uint32_t rb_bufsz, tmp; in vcn_v2_0_start() local
1054 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1055 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
Dvega20_ih.c164 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega20_ih_rb_cntl() local
172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega20_ih_rb_cntl()
Dnavi10_ih.c214 int rb_bufsz = order_base_2(ih->ring_size / 4); in navi10_ih_rb_cntl() local
222 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in navi10_ih_rb_cntl()
Dsdma_v2_4.c416 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
440 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
442 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
Dcik_sdma.c438 u32 rb_bufsz; in cik_sdma_gfx_resume() local
464 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
465 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
Dvcn_v3_0.c960 uint32_t rb_bufsz, tmp; in vcn_v3_0_start_dpg_mode() local
1060 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start_dpg_mode()
1061 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start_dpg_mode()
1114 uint32_t rb_bufsz, tmp; in vcn_v3_0_start() local
1247 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start()
1248 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start()
Dgfx_v6_0.c2090 u32 rb_bufsz; in gfx_v6_0_cp_gfx_resume() local
2106 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_gfx_resume()
2107 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_gfx_resume()
2187 u32 rb_bufsz; in gfx_v6_0_cp_compute_resume() local
2195 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2196 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
2215 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2216 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()

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