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Searched refs:pll_base (Results 1 – 19 of 19) sorted by relevance

/Linux-v5.15/arch/mips/ath79/
Dclock.c93 static void __init ar71xx_clocks_init(void __iomem *pll_base) in ar71xx_clocks_init() argument
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
124 static void __init ar724x_clocks_init(void __iomem *pll_base) in ar724x_clocks_init() argument
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
144 static void __init ar933x_clocks_init(void __iomem *pll_base) in ar933x_clocks_init() argument
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init()
178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); in ar933x_clocks_init()
232 static void __init ar934x_clocks_init(void __iomem *pll_base) in ar934x_clocks_init() argument
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
[all …]
/Linux-v5.15/drivers/clk/imx/
Dclk-imx5.c283 void __iomem *pll_base; in mx50_clocks_init() local
286 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); in mx50_clocks_init()
287 WARN_ON(!pll_base); in mx50_clocks_init()
288 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx50_clocks_init()
290 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); in mx50_clocks_init()
291 WARN_ON(!pll_base); in mx50_clocks_init()
292 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx50_clocks_init()
294 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); in mx50_clocks_init()
295 WARN_ON(!pll_base); in mx50_clocks_init()
296 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx50_clocks_init()
[all …]
/Linux-v5.15/drivers/video/fbdev/omap2/omapfb/dss/
Dvideo-pll.c133 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
140 pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]); in dss_video_pll_init()
141 if (IS_ERR(pll_base)) { in dss_video_pll_init()
143 return ERR_CAST(pll_base); in dss_video_pll_init()
175 pll->base = pll_base; in dss_video_pll_init()
Ddsi.c294 void __iomem *pll_base; member
440 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
456 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
5218 pll->base = dsi->pll_base; in dsi_init_pll_data()
5343 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, in dsi_bind()
5345 if (!dsi->pll_base) { in dsi_bind()
/Linux-v5.15/drivers/gpu/drm/omapdrm/dss/
Dvideo-pll.c142 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
150 pll_base = devm_ioremap_resource(&pdev->dev, res); in dss_video_pll_init()
151 if (IS_ERR(pll_base)) in dss_video_pll_init()
152 return ERR_CAST(pll_base); in dss_video_pll_init()
183 pll->base = pll_base; in dss_video_pll_init()
Ddsi.h343 void __iomem *pll_base; member
Ddsi.c94 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
108 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
4537 pll->base = dsi->pll_base; in dsi_init_pll_data()
4930 dsi->pll_base = devm_ioremap_resource(dev, res); in dsi_probe()
4931 if (IS_ERR(dsi->pll_base)) in dsi_probe()
4932 return PTR_ERR(dsi->pll_base); in dsi_probe()
/Linux-v5.15/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_28nm.c85 val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_STATUS); in pll_28nm_poll_for_ready()
100 void __iomem *base = pll_28nm->phy->pll_base; in pll_28nm_software_reset()
119 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
243 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_recalc_rate()
290 void __iomem *base = pll_28nm->phy->pll_base; in _dsi_pll_28nm_vco_prepare_hpm()
384 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare_lp()
438 dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); in dsi_pll_28nm_vco_unprepare()
482 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_save_state()
499 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_restore_state()
550 pll_28nm->phy->pll_base + in pll_28nm_register()
[all …]
Ddsi_phy_28nm_8960.c77 val = dsi_phy_read(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_RDY); in pll_28nm_poll_for_ready()
97 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate()
146 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_recalc_rate()
180 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_vco_prepare()
233 dsi_phy_write(pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); in dsi_pll_28nm_vco_unprepare()
347 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_save_state()
363 void __iomem *base = pll_28nm->phy->pll_base; in dsi_28nm_pll_restore_state()
428 bytediv->reg = pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; in pll_28nm_register()
448 parent_name, 0, pll_28nm->phy->pll_base + in pll_28nm_register()
Ddsi_phy_10nm.c173 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit()
197 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg()
223 void __iomem *base = pll->phy->pll_base; in dsi_pll_commit()
278 rc = readl_poll_timeout_atomic(pll->phy->pll_base + in dsi_pll_10nm_lock_status()
295 dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); in dsi_pll_disable_pll_bias()
307 dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); in dsi_pll_enable_pll_bias()
409 void __iomem *base = pll_10nm->phy->pll_base; in dsi_pll_10nm_vco_recalc_rate()
476 cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base + in dsi_10nm_pll_save_state()
500 val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_10nm_pll_restore_state()
503 dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); in dsi_10nm_pll_restore_state()
[all …]
Ddsi_phy_7nm.c175 void __iomem *base = pll->phy->pll_base; in dsi_pll_ssc_commit()
199 void __iomem *base = pll->phy->pll_base; in dsi_pll_config_hzindep_reg()
241 dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); in dsi_pll_config_hzindep_reg()
247 void __iomem *base = pll->phy->pll_base; in dsi_pll_commit()
299 rc = readl_poll_timeout_atomic(pll->phy->pll_base + in dsi_pll_7nm_lock_status()
316 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0); in dsi_pll_disable_pll_bias()
326 dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0); in dsi_pll_enable_pll_bias()
437 void __iomem *base = pll_7nm->phy->pll_base; in dsi_pll_7nm_vco_recalc_rate()
504 cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base + in dsi_7nm_pll_save_state()
528 val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE); in dsi_7nm_pll_restore_state()
[all …]
Ddsi_phy_14nm.c114 void __iomem *base = pll_14nm->phy->pll_base; in pll_14nm_poll_for_ready()
288 void __iomem *base = pll->phy->pll_base; in pll_db_commit_ssc()
323 void __iomem *base = pll->phy->pll_base; in pll_db_commit_common()
387 void __iomem *base = pll->phy->pll_base; in pll_db_commit_14nm()
496 void __iomem *base = pll_14nm->phy->pll_base; in dsi_pll_14nm_vco_recalc_rate()
535 void __iomem *base = pll_14nm->phy->pll_base; in dsi_pll_14nm_vco_prepare()
741 void __iomem *base = phy->pll_base; in dsi_14nm_set_usecase()
Ddsi_phy.h87 void __iomem *pll_base; member
Ddsi_phy.c717 phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", "DSI_PLL", &phy->pll_size); in dsi_phy_driver_probe()
718 if (IS_ERR(phy->pll_base)) { in dsi_phy_driver_probe()
936 phy->pll_size, phy->pll_base, in msm_dsi_phy_snapshot()
/Linux-v5.15/drivers/clk/
Dclk-bm1880.c63 void __iomem *pll_base; member
538 void __iomem *pll_base = data->pll_base; in bm1880_clk_register_plls() local
544 hw = bm1880_clk_register_pll(bm1880_clk, pll_base); in bm1880_clk_register_plls()
893 void __iomem *pll_base, *sys_base; in bm1880_clk_probe() local
899 pll_base = devm_ioremap_resource(&pdev->dev, res); in bm1880_clk_probe()
900 if (IS_ERR(pll_base)) in bm1880_clk_probe()
901 return PTR_ERR(pll_base); in bm1880_clk_probe()
919 clk_data->pll_base = pll_base; in bm1880_clk_probe()
/Linux-v5.15/arch/arm/mach-tegra/
Dsleep-tegra20.S55 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
56 ldr \rd, [\r_car_base, #\pll_base]
65 .macro pll_enable, rd, r_car_base, pll_base, test_mask
69 ldr \rd, [\r_car_base, #\pll_base]
72 streq \rd, [\r_car_base, #\pll_base]
Dsleep-tegra30.S102 .macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask
103 ldr \rd, [\r_car_base, #\pll_base]
130 .macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask
134 ldr \rd, [\r_car_base, #\pll_base]
137 streq \rd, [\r_car_base, #\pll_base]
151 .macro pll_locked, rd, r_car_base, pll_base, test_mask
155 ldr \rd, [\r_car_base, #\pll_base]
/Linux-v5.15/Documentation/devicetree/bindings/display/msm/
Dedp.txt9 * "pll_base"
33 "pll_base";
/Linux-v5.15/drivers/clk/st/
Dclkgen-pll.c755 void __iomem *pll_base; in clkgen_c32_pll_setup() local
765 pll_base = clkgen_get_register_base(np); in clkgen_c32_pll_setup()
766 if (!pll_base) in clkgen_c32_pll_setup()
771 clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags, in clkgen_c32_pll_setup()
808 clk = clkgen_odf_register(pll_name, pll_base, datac->data, in clkgen_c32_pll_setup()