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Searched refs:mmCGTS_SM_CTRL_REG (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c79 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
210 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
Dsi.c535 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
634 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
732 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
812 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
892 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
Dgfx_v8_0.c302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
5501 data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_get_clockgating_state()
5697 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5708 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
5739 temp = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v8_0_update_medium_grain_clock_gating()
5743 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v8_0_update_medium_grain_clock_gating()
Dgfx_v6_0.c2608 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2611 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
2643 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v6_0_enable_mgcg()
2646 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v6_0_enable_mgcg()
Dgfx_v7_0.c3663 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3675 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
3695 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3698 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h298 #define mmCGTS_SM_CTRL_REG 0x2454 macro
Dgfx_7_0_d.h1480 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_7_2_d.h1501 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_8_0_d.h1694 #define mmCGTS_SM_CTRL_REG 0xf000 macro
Dgfx_8_1_d.h1662 #define mmCGTS_SM_CTRL_REG 0xf000 macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6303 #define mmCGTS_SM_CTRL_REG … macro
Dgc_9_1_offset.h6525 #define mmCGTS_SM_CTRL_REG … macro
Dgc_9_2_1_offset.h6537 #define mmCGTS_SM_CTRL_REG … macro