Searched refs:dcn3_01_soc (Results 1 – 1 of 1) sorted by relevance
168 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = { variable1495 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; in init_soc_bounding_box()1514 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in init_soc_bounding_box()1517 dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; in init_soc_bounding_box()1520 dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; in init_soc_bounding_box()1583 dcn3_01_soc.num_chans = bw_params->num_channels; in dcn301_update_bw_bounding_box()1588 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()1589 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_update_bw_bounding_box()1601 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn301_update_bw_bounding_box()1602 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_update_bw_bounding_box()[all …]
