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/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/Linux-v5.15/arch/arm/boot/dts/
Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
[all …]
Dimx7d-remarkable2.dts48 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
50 assigned-clock-parents = <&clks IMX7D_CKIL>;
51 assigned-clock-rates = <0>, <32768>;
61 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
62 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
69 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
70 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
107 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
108 assigned-clock-rates = <400000000>;
Dexynos4412-odroid-common.dtsi126 assigned-clocks = <&clock CLK_FOUT_EPLL>;
127 assigned-clock-rates = <45158401>;
131 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
137 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
140 assigned-clock-rates = <0>, <0>,
208 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
210 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
211 assigned-clock-rates = <0>, <176000000>;
216 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
218 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
121 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-rates = <0>, <100000000>;
278 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
280 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281 assigned-clock-rates = <0>, <24576000>;
313 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
Dimx7d-sdb.dts222 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
224 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
225 assigned-clock-rates = <0>, <100000000>;
249 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
251 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
252 assigned-clock-rates = <0>, <100000000>;
393 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
396 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
397 assigned-clock-rates = <0>, <884736000>, <12288000>;
429 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
[all …]
Dimx7s-warp.dts84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
271 assigned-clock-rates = <0>, <36864000>;
278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
Dexynos4412-itop-elite.dts130 assigned-clocks = <&clock CLK_MOUT_CAM0>;
131 assigned-clock-parents = <&clock CLK_XUSBXTI>;
135 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
139 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
141 assigned-clock-rates = <0>, <0>, <112896000>, <11289600>;
159 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
161 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
162 assigned-clock-rates = <0>, <176000000>;
Dimx7d-nitrogen7.dts114 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
116 assigned-clock-parents = <&clks IMX7D_CKIL>;
117 assigned-clock-rates = <0>, <32768>;
131 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
134 assigned-clock-rates = <0>, <100000000>;
322 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
323 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
330 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
331 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/ti/
Dk3-j721e-common-proc-board.dts513 assigned-clocks = <&k3_clks 157 371>;
514 assigned-clock-parents = <&k3_clks 157 400>;
515 assigned-clock-rates = <24576000>; /* for 48KHz */
567 assigned-clocks = <&k3_clks 152 1>,
571 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
644 assigned-clocks = <&wiz0_pll1_refclk>;
645 assigned-clock-parents = <&cmn_refclk1>;
649 assigned-clocks = <&wiz0_refclk_dig>;
650 assigned-clock-parents = <&cmn_refclk1>;
654 assigned-clocks = <&wiz1_pll1_refclk>;
[all …]
/Linux-v5.15/arch/mips/boot/dts/img/
Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/Linux-v5.15/drivers/s390/char/
Dsclp_cmd.c243 u16 assigned; member
266 for (i = 0; i < sccb->assigned; i++) { in sclp_attach_storage()
425 static void __init insert_increment(u16 rn, int standby, int assigned) in insert_increment() argument
439 if (assigned && incr->rn > rn) in insert_increment()
441 if (!assigned && incr->rn - last_rn > 1) in insert_increment()
446 if (!assigned) in insert_increment()
458 int i, id, assigned, rc; in sclp_detect_standby_memory() local
468 assigned = 0; in sclp_detect_standby_memory()
478 for (i = 0; i < sccb->assigned; i++) { in sclp_detect_standby_memory()
481 assigned++; in sclp_detect_standby_memory()
[all …]
/Linux-v5.15/arch/arm64/boot/dts/freescale/
Dimx8mp.dtsi414 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
423 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
430 assigned-clock-rates = <0>, <0>,
598 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
599 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
600 assigned-clock-rates = <40000000>;
613 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
614 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
615 assigned-clock-rates = <40000000>;
789 assigned-clock-rates = <80000000>;
[all …]
Dimx8mq.dtsi519 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
523 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
526 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
619 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
627 assigned-clock-rates = <0>, <0>,
634 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
998 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1001 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1003 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1037 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
[all …]
Dimx8-ss-dma.dtsi116 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
117 assigned-clock-rates = <24000000>;
127 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
128 assigned-clock-rates = <24000000>;
138 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
139 assigned-clock-rates = <24000000>;
149 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
150 assigned-clock-rates = <24000000>;
Dimx8mq-sr-som.dtsi163 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
164 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
165 assigned-clock-rates = <25000000>;
172 assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
173 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
174 assigned-clock-rates = <80000000>;
179 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
180 assigned-clock-rates = <400000000>;
Dimx8mn-evk.dtsi164 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
165 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
166 assigned-clock-rates = <24576000>;
178 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
179 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
180 assigned-clock-rates = <24576000>;
209 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
210 assigned-clock-rates = <200000000>;
222 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
223 assigned-clock-rates = <400000000>;
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47 assigned-clock-rates = <50000000>;
70 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71 assigned-clock-rates = <50000000>;
/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt14 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
15 - assigned-clock-parents: parent of mux clock.
31 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
32 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
/Linux-v5.15/Documentation/devicetree/bindings/pwm/
Dpwm-sprd.txt16 - assigned-clocks: Reference to the PWM clock entries.
17 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
31 assigned-clocks = <&aon_clk CLK_PWM0>,
35 assigned-clock-parents = <&ext_26m>,
/Linux-v5.15/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt76 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
81 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
84 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
106 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
107 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
127 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
128 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
/Linux-v5.15/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211 assigned-clock-rates = <1536000>;
223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225 assigned-clock-rates = <1536000>;
237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
[all …]

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