Searched refs:RREG64_PCIE (Results 1 – 5 of 5) sorted by relevance
93 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()110 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_7_querry_uncorrectable_error_count()218 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_address()239 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); in umc_v6_7_query_error_address()
144 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()161 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v8_7_querry_uncorrectable_error_count()212 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v8_7_query_error_address()230 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); in umc_v8_7_query_error_address()
34 uint64_t mc_status = RREG64_PCIE(mc_status_addr * 4); in amdgpu_mca_query_correctable_error_count()45 uint64_t mc_status = RREG64_PCIE(mc_status_addr * 4); in amdgpu_mca_query_uncorrectable_error_count()
219 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()244 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_1_querry_uncorrectable_error_count()320 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_1_query_error_address()338 err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); in umc_v6_1_query_error_address()
1182 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) macro
