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Searched refs:MCLK (Results 1 – 25 of 52) sorted by relevance

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/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dmt8173-rt5650.txt16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
Dcs42l56.txt20 Frequency = MCLK / 4 * (N+2)
22 MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
Dtas2552.txt18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
Dmaxim,max98088.txt12 - clocks: the clock provider of MCLK, see ../clock/clock-bindings.txt section
Dmax9860.txt14 - clocks : A clock specifier for the clock connected as MCLK.
Dda7213.txt10 - clocks : phandle and clock specifier for codec MCLK.
Dcs4271.txt24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
Dtas571x.txt22 - clocks: clock phandle for the MCLK input
Dcs43130.txt20 When external MCLK is generated by external crystal
Drt5682.txt38 - clocks : phandle and clock specifier for codec MCLK.
Domap-abe-twl6040.txt6 - ti,mclk-freq: MCLK frequency for HPPLL operation
Dnau8825.txt76 - clock-names: should include "mclk" for the MCLK master clock
/Linux-v5.15/Documentation/devicetree/bindings/media/
Dpxa-camera.txt12 sensor master clock MCLK
13 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
/Linux-v5.15/sound/soc/meson/
Daiu-encoder-spdif.c144 ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate); in aiu_encoder_spdif_hw_params()
183 ret = clk_set_parent(aiu->spdif.clks[MCLK].clk, in aiu_encoder_spdif_startup()
Daiu.h20 MCLK, enumerator
Daiu-encoder-i2s.c185 fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate); in aiu_encoder_i2s_set_clocks()
311 ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq); in aiu_encoder_i2s_set_sysclk()
Daiu.c205 [MCLK] = "i2s_mclk",
212 [MCLK] = "spdif_mclk_sel"
/Linux-v5.15/Documentation/sound/soc/
Dclocking.rst12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
34 - BCLK = MCLK / x, or
/Linux-v5.15/drivers/spi/
Dspi-mpc52xx-psc.c27 #define MCLK 20000000 /* PSC port MClk in hz */ macro
104 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
106 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
315 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; in mpc52xx_psc_spi_port_config()
/Linux-v5.15/drivers/media/pci/ddbridge/
Dddbridge-sx8.c23 static const u32 MCLK = (1550000000 / 12); variable
196 if (p->symbol_rate >= (MCLK / 2)) in start()
218 if (p->symbol_rate >= MCLK / 2) { in start()
253 i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7; in start()
/Linux-v5.15/Documentation/devicetree/bindings/display/bridge/
Dsii902x.txt31 Describes SII902x MCLK input. MCLK can be used to produce
/Linux-v5.15/arch/arm/boot/dts/
Dstm32mp15xx-dkx.dtsi77 "Playback" , "MCLK",
78 "Capture" , "MCLK",
213 clock-names = "MCLK";
523 clock-names = "sai_ck", "MCLK";
/Linux-v5.15/Documentation/devicetree/bindings/mfd/
Dtwl6040.txt23 - clock-names: Must be "clk32k" for the 32K clock and "mclk" for the MCLK.
/Linux-v5.15/drivers/video/fbdev/sis/
Dinit.c2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2281 idx1 = longtemp % (MCLK * 16); in SiS_DoCalcDelay()
2282 longtemp /= (MCLK * 16); in SiS_DoCalcDelay()
2289 unsigned short colordepth, unsigned short MCLK) in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2324 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; in SiS_SetCRT1FIFO_300()
/Linux-v5.15/arch/arm/mm/
Dproc-sa110.S94 ldr r1, [r1, #0] @ force switch to MCLK

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