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Searched refs:FIELD_PREP (Results 1 – 25 of 391) sorted by relevance

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/Linux-v5.15/drivers/misc/habanalabs/include/gaudi/
Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
[all …]
/Linux-v5.15/drivers/iio/adc/
Dstm32-dfsdm.h48 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
50 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
52 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
54 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
56 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
58 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
60 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
62 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
64 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
66 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
[all …]
/Linux-v5.15/drivers/phy/microchip/
Dsparx5_serdes_regs.h36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
48 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
57 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
63 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
69 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
75 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
81 FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
90 FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
99 FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
[all …]
/Linux-v5.15/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main_regs.h61 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
67 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
76 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
91 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
106 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
115 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
121 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
127 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
136 FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x)
145 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
[all …]
/Linux-v5.15/drivers/infiniband/hw/irdma/
Duda.c31 qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | in irdma_sc_access_ah()
32 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | in irdma_sc_access_ah()
33 FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); in irdma_sc_access_ah()
35 qw2 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ARPINDEX, info->dst_arpindex) | in irdma_sc_access_ah()
36 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_FLOWLABEL, info->flow_label) | in irdma_sc_access_ah()
37 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | in irdma_sc_access_ah()
38 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXHI, info->pd_idx >> 16); in irdma_sc_access_ah()
42 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) | in irdma_sc_access_ah()
43 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1])); in irdma_sc_access_ah()
45 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) | in irdma_sc_access_ah()
[all …]
Dctrl.c170 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_add_arp_cache_entry()
171 FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, (info->permanent ? 1 : 0)) | in irdma_sc_add_arp_cache_entry()
172 FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, 1) | in irdma_sc_add_arp_cache_entry()
173 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_add_arp_cache_entry()
205 FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | in irdma_sc_del_arp_cache_entry()
206 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_del_arp_cache_entry()
241 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | in irdma_sc_manage_apbvt_entry()
242 FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | in irdma_sc_manage_apbvt_entry()
243 FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); in irdma_sc_manage_apbvt_entry()
292 qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | in irdma_sc_manage_qhash_table_entry()
[all …]
Duk.c21 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->tag_off)); in irdma_set_fragment()
23 FIELD_PREP(IRDMAQPSQ_VALID, valid) | in irdma_set_fragment()
24 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->len) | in irdma_set_fragment()
25 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->stag)); in irdma_set_fragment()
29 FIELD_PREP(IRDMAQPSQ_VALID, valid)); in irdma_set_fragment()
45 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->tag_off)); in irdma_set_fragment_gen_1()
47 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->len) | in irdma_set_fragment_gen_1()
48 FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->stag)); in irdma_set_fragment_gen_1()
78 hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | in irdma_nop_1()
79 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, signaled) | in irdma_nop_1()
[all …]
/Linux-v5.15/drivers/net/wireless/ath/ath11k/
Dhal_tx.c42 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); in ath11k_hal_tx_cmd_desc_setup()
44 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, in ath11k_hal_tx_cmd_desc_setup()
47 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, in ath11k_hal_tx_cmd_desc_setup()
49 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); in ath11k_hal_tx_cmd_desc_setup()
52 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | in ath11k_hal_tx_cmd_desc_setup()
53 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | in ath11k_hal_tx_cmd_desc_setup()
54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, in ath11k_hal_tx_cmd_desc_setup()
56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, in ath11k_hal_tx_cmd_desc_setup()
58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, in ath11k_hal_tx_cmd_desc_setup()
60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, in ath11k_hal_tx_cmd_desc_setup()
[all …]
Dhal_rx.c16 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) | in ath11k_hal_reo_set_desc_hdr()
17 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type); in ath11k_hal_reo_set_desc_hdr()
20 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic); in ath11k_hal_reo_set_desc_hdr()
28 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) | in ath11k_hal_reo_cmd_queue_stats()
29 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_queue_stats()
40 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI, in ath11k_hal_reo_cmd_queue_stats()
61 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) | in ath11k_hal_reo_cmd_flush_cache()
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_flush_cache()
73 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI, in ath11k_hal_reo_cmd_flush_cache()
82 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX, in ath11k_hal_reo_cmd_flush_cache()
[all …]
/Linux-v5.15/drivers/phy/amlogic/
Dphy-meson-g12a-usb2.c187 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
188 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | in phy_meson_g12a_usb2_init()
190 FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | in phy_meson_g12a_usb2_init()
196 FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) | in phy_meson_g12a_usb2_init()
197 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) | in phy_meson_g12a_usb2_init()
198 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) | in phy_meson_g12a_usb2_init()
199 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | in phy_meson_g12a_usb2_init()
200 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); in phy_meson_g12a_usb2_init()
202 value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | in phy_meson_g12a_usb2_init()
203 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | in phy_meson_g12a_usb2_init()
[all …]
/Linux-v5.15/drivers/crypto/ccree/
Dcc_hw_queue_defs.h224 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); in set_queue_last_ind_bit()
242 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr)); in set_din_type()
244 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | in set_din_type()
245 FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_type()
246 FIELD_PREP(WORD1_NS_BIT, axi_sec); in set_din_type()
260 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); in set_din_no_dma()
273 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE); in set_cpp_crypto_key()
274 pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); in set_cpp_crypto_key()
276 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot); in set_cpp_crypto_key()
291 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_sram()
[all …]
/Linux-v5.15/drivers/i3c/master/mipi-i3c-hci/
Dcmd_v1.c23 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v)
28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
36 #define CMD_0_ATTR_I FIELD_PREP(CMD_0_ATTR, 0x1)
38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v)
39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v)
40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v)
41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v)
[all …]
Dcmd_v2.c24 #define CMD_0_ATTR_U FIELD_PREP(CMD_0_ATTR, 0x4)
26 #define CMD_U3_HDR_TSP_ML_CTRL(v) FIELD_PREP(W3_MASK(107, 104), v)
27 #define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v)
28 #define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v)
29 #define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v)
30 #define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v)
31 #define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v)
32 #define CMD_U2_BT_CMD2(v) FIELD_PREP(W2_MASK( 87, 80), v)
33 #define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v)
34 #define CMD_U2_BT_CMD1(v) FIELD_PREP(W2_MASK( 79, 72), v)
[all …]
/Linux-v5.15/drivers/gpu/drm/meson/
Dmeson_overlay.c27 #define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines)
29 #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val)
36 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
37 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
38 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
41 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
42 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
45 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
46 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
49 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value)
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt76x2/
Dusb_phy.c64 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2u_phy_set_channel()
65 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2u_phy_set_channel()
66 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
67 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
68 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), in mt76x2u_phy_set_channel()
69 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2u_phy_set_channel()
70 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2u_phy_set_channel()
71 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
72 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
73 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), in mt76x2u_phy_set_channel()
[all …]
Dinit.c57 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
58 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
59 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
63 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
64 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
65 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
69 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
70 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \ in mt76_write_mac_initvals()
71 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
72 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
[all …]
Dpci_phy.c126 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2_phy_set_channel()
127 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2_phy_set_channel()
128 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
129 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
130 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), in mt76x2_phy_set_channel()
131 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2_phy_set_channel()
132 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2_phy_set_channel()
133 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
134 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
135 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), in mt76x2_phy_set_channel()
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7603/
Dinit.c27 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), in mt7603_set_tmac_template()
60 FIELD_PREP(MT_PSE_FRP_P0, 7) | in mt7603_dma_sched_init()
61 FIELD_PREP(MT_PSE_FRP_P1, 6) | in mt7603_dma_sched_init()
62 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); in mt7603_dma_sched_init()
122 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | in mt7603_phy_init()
123 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); in mt7603_phy_init()
152 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | in mt7603_mac_init()
153 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | in mt7603_mac_init()
154 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | in mt7603_mac_init()
155 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); in mt7603_mac_init()
[all …]
/Linux-v5.15/drivers/media/platform/allegro-dvt/
Dallegro-mail.c98 dst[i++] = FIELD_PREP(GENMASK(31, 16), param->height) | in allegro_encode_config_blob()
99 FIELD_PREP(GENMASK(15, 0), param->width); in allegro_encode_config_blob()
108 dst[i++] = FIELD_PREP(GENMASK(31, 24), codec) | in allegro_encode_config_blob()
109 FIELD_PREP(GENMASK(23, 8), param->constraint_set_flags) | in allegro_encode_config_blob()
110 FIELD_PREP(GENMASK(7, 0), param->profile); in allegro_encode_config_blob()
111 dst[i++] = FIELD_PREP(GENMASK(31, 16), param->tier) | in allegro_encode_config_blob()
112 FIELD_PREP(GENMASK(15, 0), param->level); in allegro_encode_config_blob()
116 val |= FIELD_PREP(GENMASK(7, 4), param->log2_max_frame_num); in allegro_encode_config_blob()
118 val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc - 1); in allegro_encode_config_blob()
120 val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc); in allegro_encode_config_blob()
[all …]
/Linux-v5.15/drivers/fpga/
Ddfl-n3000-nios.c104 (FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \
106 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \
108 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK, \
110 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK, \
112 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK, \
114 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK, \
116 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK, \
118 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK, \
122 (FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \
124 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \
[all …]
/Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-ingenic.c95 val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) | in jz4775_mac_set_mode()
96 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII); in jz4775_mac_set_mode()
101 val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) | in jz4775_mac_set_mode()
102 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII); in jz4775_mac_set_mode()
107 val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) | in jz4775_mac_set_mode()
108 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); in jz4775_mac_set_mode()
116 val = FIELD_PREP(MACPHYC_TXCLK_SEL_MASK, MACPHYC_TXCLK_SEL_INPUT) | in jz4775_mac_set_mode()
117 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII); in jz4775_mac_set_mode()
155 val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); in x1600_mac_set_mode()
175 val = FIELD_PREP(MACPHYC_MODE_SEL_MASK, MACPHYC_MODE_SEL_RMII) | in x1830_mac_set_mode()
[all …]
Ddwmac-mediatek.c181 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
182 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
183 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
185 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
186 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
187 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
196 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
197 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
198 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
200 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
[all …]
/Linux-v5.15/drivers/net/ethernet/mellanox/mlxbf_gige/
Dmlxbf_gige_mdio.c67 #define MLXBF_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \
68 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \
69 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \
70 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDC_PERIOD_MASK, \
72 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \
73 FIELD_PREP(MLXBF_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
80 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_AD_MASK, data); in mlxbf_gige_mdio_create_cmd()
81 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_DEVAD_MASK, phy_reg); in mlxbf_gige_mdio_create_cmd()
82 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_PARTAD_MASK, phy_add); in mlxbf_gige_mdio_create_cmd()
83 gw_reg |= FIELD_PREP(MLXBF_GIGE_MDIO_GW_OPCODE_MASK, opcode); in mlxbf_gige_mdio_create_cmd()
[all …]
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7615/
Dusb_sdio.c84 w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rate->bw); in mt7663_usb_sdio_set_rates()
91 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rate->bw) | in mt7663_usb_sdio_set_rates()
92 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, in mt7663_usb_sdio_set_rates()
98 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rate->probe_val) | in mt7663_usb_sdio_set_rates()
99 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rate->val[0]) | in mt7663_usb_sdio_set_rates()
100 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rate->val[1])); in mt7663_usb_sdio_set_rates()
103 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rate->val[1] >> 8) | in mt7663_usb_sdio_set_rates()
104 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rate->val[1]) | in mt7663_usb_sdio_set_rates()
105 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rate->val[2]) | in mt7663_usb_sdio_set_rates()
106 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rate->val[2])); in mt7663_usb_sdio_set_rates()
[all …]
/Linux-v5.15/drivers/phy/ralink/
Dphy-mt7621-pci.c132 FIELD_PREP(RG_PE1_H_XTAL_TYPE, 0x00)); in mt7621_set_phy_for_ssc()
146 FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x01)); in mt7621_set_phy_for_ssc()
151 FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00)); in mt7621_set_phy_for_ssc()
156 FIELD_PREP(RG_PE1_H_PLL_FBKSEL, 0x01)); in mt7621_set_phy_for_ssc()
161 FIELD_PREP(RG_PE1_H_LCDDS_SSC_PRD, 0x00)); in mt7621_set_phy_for_ssc()
166 FIELD_PREP(RG_PE1_H_LCDDS_SSC_PRD, 0x18d)); in mt7621_set_phy_for_ssc()
172 FIELD_PREP(RG_PE1_H_LCDDS_SSC_DELTA, 0x4a) | in mt7621_set_phy_for_ssc()
173 FIELD_PREP(RG_PE1_H_LCDDS_SSC_DELTA1, 0x4a)); in mt7621_set_phy_for_ssc()
178 FIELD_PREP(RG_PE1_H_PLL_PREDIV, 0x00)); in mt7621_set_phy_for_ssc()
191 FIELD_PREP(RG_PE1_H_PLL_BC, 0x02) | in mt7621_set_phy_for_ssc()
[all …]

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