Home
last modified time | relevance | path

Searched refs:DPIO_PHY0 (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gvt/
Dhandlers.c542 enum dpio_phy phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
554 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
558 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate()
1877 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in bxt_gt_disp_pwron_write()
1879 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in bxt_gt_disp_pwron_write()
3475 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, in init_bxt_mmio_info()
3489 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT); in init_bxt_mmio_info()
3490 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT); in init_bxt_mmio_info()
3491 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT); in init_bxt_mmio_info()
3492 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT); in init_bxt_mmio_info()
[all …]
Ddisplay.c231 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change()
235 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change()
294 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
296 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
324 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change()
326 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
Dmmio.c260 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
264 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_display_power.c1545 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1546 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | in assert_chv_phy_status()
1547 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status()
1548 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status()
1549 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status()
1550 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status()
1551 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status()
1559 phy_status |= PHY_POWERGOOD(DPIO_PHY0); in assert_chv_phy_status()
1562 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) in assert_chv_phy_status()
1563 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
[all …]
Dintel_dpio_phy.c162 [DPIO_PHY0] = {
184 [DPIO_PHY0] = {
265 *phy = DPIO_PHY0; in bxt_port_to_phy_channel()
808 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable()
956 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
Dintel_display.h284 DPIO_PHY0, enumerator
Dintel_display_types.h1732 return DPIO_PHY0; in vlv_dig_port_to_phy()
/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_sideband.c241 return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO; in vlv_dpio_phy_iosf_port()
Di915_reg.h3522 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))