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Searched refs:CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT (Results 1 – 2 of 2) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_sh_mask.h2516 #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT … macro
Dgc_10_3_0_sh_mask.h16438 #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT … macro