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Searched refs:CLK_TOP_AUD_ENGEN2_SEL (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.15/include/dt-bindings/clock/
Dmt8516-clk.h179 #define CLK_TOP_AUD_ENGEN2_SEL 147 macro
Dmt8192-clk.h56 #define CLK_TOP_AUD_ENGEN2_SEL 44 macro
/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt8516.c399 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
Dclk-mt8167.c589 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
Dclk-mt8192.c810 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",