Searched refs:CLK_TOP_AUD_2_SEL (Results 1 – 7 of 7) sorted by relevance
| /Linux-v5.15/include/dt-bindings/clock/ |
| D | mt8173-clk.h | 120 #define CLK_TOP_AUD_2_SEL 110 macro
|
| D | mt2712-clk.h | 157 #define CLK_TOP_AUD_2_SEL 126 macro
|
| D | mt8192-clk.h | 60 #define CLK_TOP_AUD_2_SEL 48 macro
|
| /Linux-v5.15/drivers/clk/mediatek/ |
| D | clk-mt8173.c | 581 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
|
| D | clk-mt2712.c | 799 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
|
| D | clk-mt8192.c | 819 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
|
| /Linux-v5.15/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 883 <&topckgen CLK_TOP_AUD_2_SEL>;
|
