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Searched refs:CLK_TOP_APLL12_DIV5 (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/include/dt-bindings/clock/
Dmt8516-clk.h157 #define CLK_TOP_APLL12_DIV5 125 macro
Dmt6779-clk.h144 #define CLK_TOP_APLL12_DIV5 134 macro
Dmt8192-clk.h160 #define CLK_TOP_APLL12_DIV5 148 macro
/Linux-v5.15/sound/soc/mediatek/mt8192/
Dmt8192-afe-clk.h212 CLK_TOP_APLL12_DIV5, enumerator
Dmt8192-afe-clk.c55 [CLK_TOP_APLL12_DIV5] = "top_apll12_div5",
501 .div_clk_id = CLK_TOP_APLL12_DIV5,
/Linux-v5.15/drivers/clk/mediatek/
Dclk-mt8516.c672 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
Dclk-mt8167.c918 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
Dclk-mt6779.c839 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
Dclk-mt8192.c867 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),