| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_vcn.h | 70 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
76 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
80 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
88 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
|
| D | vcn_v1_0.c | 630 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) in vcn_v1_0_clock_gating_dpg_mode() argument
641 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
643 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
672 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
675 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
678 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
681 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
|
| D | vcn_v2_0.c | 588 uint8_t sram_sel, uint8_t indirect) in vcn_v2_0_clock_gating_dpg_mode() argument
620 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
624 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
628 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
632 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
|
| D | vcn_v2_5.c | 655 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v2_5_clock_gating_dpg_mode() argument
687 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
691 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
695 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
699 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
|
| D | vcn_v3_0.c | 788 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v3_0_clock_gating_dpg_mode() argument
820 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
824 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
828 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
832 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
|
