Searched refs:seq_state (Results 1 – 9 of 9) sorted by relevance
941 const char *seq_state; in cia_decode_mem_error() local976 seq_state = "Idle"; in cia_decode_mem_error()979 seq_state = "DMA READ or DMA WRITE"; in cia_decode_mem_error()982 seq_state = "READ MISS (or READ MISS MODIFY) with victim"; in cia_decode_mem_error()985 seq_state = "READ MISS (or READ MISS MODIFY) with no victim"; in cia_decode_mem_error()988 seq_state = "Refresh"; in cia_decode_mem_error()991 seq_state = "Idle, waiting for DMA pending read"; in cia_decode_mem_error()994 seq_state = "Idle, ras precharge"; in cia_decode_mem_error()997 seq_state = "Unknown"; in cia_decode_mem_error()1027 printk(KERN_CRIT " Memory sequencer state: %s\n", seq_state); in cia_decode_mem_error()
216 u32 stat, seq_state; in boot_core() local255 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; in boot_core()256 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); in boot_core()259 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) in boot_core()
422 u64 seq_state; in fsi_spi_transfer_init() local438 seq_state = status & SPI_FSI_STATUS_SEQ_STATE; in fsi_spi_transfer_init()453 } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE)); in fsi_spi_transfer_init()
273 u32 seq_state; member352 u32 seq_state; member
226 config->seq_state = 0x0; in reset_store()1407 val = config->seq_state; in seq_state_show()1424 config->seq_state = val; in seq_state_store()1427 static DEVICE_ATTR_RW(seq_state);
150 writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR); in etm4_enable_hw()
886 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_irq_clean_complete() local895 switch (seq_state) { in mcr20a_irq_clean_complete()
545 :File: ``seq_state`` (rw)
189 What: /sys/bus/coresight/devices/etm<N>/seq_state
