Home
last modified time | relevance | path

Searched refs:rfHSSIPara2 (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.10/drivers/staging/rtl8723bs/hal/
Drtl8723b_rf6052.c119 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 825… in phy_RF6052_Config_ParaFile()
122 …PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255… in phy_RF6052_Config_ParaFile()
Drtl8723b_phycfg.c402 …pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parame… in phy_InitBBRFRegisterDefinition()
403 …pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parame… in phy_InitBBRFRegisterDefinition()
/Linux-v5.10/drivers/staging/rtl8188eu/hal/
Drf_cfg.c236 phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREADDREAALENGTH, 0x0); in rtl88eu_phy_rf_config()
239 phy_set_bb_reg(adapt, pphyreg->rfHSSIPara2, B3WIREDATALENGTH, 0x0); in rtl88eu_phy_rf_config()
Dbb_cfg.c608 reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in rtl88e_phy_init_bb_rf_register_definition()
609 reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in rtl88e_phy_init_bb_rf_register_definition()
Dphy.c67 tmplong2 = phy_query_bb_reg(adapt, phyreg->rfHSSIPara2, in rf_serial_read()
77 phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2); in rf_serial_read()
/Linux-v5.10/drivers/staging/rtl8192e/rtl8192e/
Dr8190P_rtl8256.c94 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, in rtl92e_config_rf()
96 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, in rtl92e_config_rf()
Dr8192E_phy.c124 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, in _rtl92e_phy_rf_read()
126 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); in _rtl92e_phy_rf_read()
127 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); in _rtl92e_phy_rf_read()
422 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
423 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
424 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
425 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; in _rtl92e_init_bb_rf_reg_def()
Dr8190P_def.h113 u32 rfHSSIPara2; member
/Linux-v5.10/drivers/staging/rtl8192u/
Dr8190_rtl8256.c152 …rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 0 to 4 bits for Z-se… in phy_rf8256_config_para_file()
153 …rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-seri… in phy_rf8256_config_para_file()
Dr819xU_phy.c165 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, in rtl8192_phy_RFSerialRead()
168 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); in rtl8192_phy_RFSerialRead()
169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); in rtl8192_phy_RFSerialRead()
615 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; in rtl8192_InitBBRFRegDef()
616 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; in rtl8192_InitBBRFRegDef()
617 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; in rtl8192_InitBBRFRegDef()
618 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; in rtl8192_InitBBRFRegDef()
Dr8192U.h625 u32 rfHSSIPara2; member
/Linux-v5.10/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_cfg.h102 u32 rfHSSIPara2; /* wire parameter control2 : */ member
/Linux-v5.10/drivers/staging/rtl8723bs/include/
Dhal_com_phycfg.h61 u32 rfHSSIPara2; /* wire parameter control2 : */ member