Searched refs:pll_state (Results 1 – 3 of 3) sorted by relevance
283 const struct intel_dpll_hw_state *pll_state, in intel_find_shared_dpll() argument305 if (memcmp(pll_state, in intel_find_shared_dpll()307 sizeof(*pll_state)) == 0) { in intel_find_shared_dpll()333 const struct intel_dpll_hw_state *pll_state) in intel_reference_shared_dpll() argument342 shared_dpll[id].hw_state = *pll_state; in intel_reference_shared_dpll()1582 const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; in skl_ddi_wrpll_get_freq() local1586 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_ddi_wrpll_get_freq()1587 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_ddi_wrpll_get_freq()1589 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) in skl_ddi_wrpll_get_freq()1590 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; in skl_ddi_wrpll_get_freq()[all …]
671 int pll_state; in stm32f4_pll_set_rate() local673 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_set_rate()675 if (pll_state) in stm32f4_pll_set_rate()684 if (pll_state) in stm32f4_pll_set_rate()721 int pll_state, ret; in stm32f4_pll_div_set_rate() local726 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()728 if (pll_state) in stm32f4_pll_div_set_rate()733 if (pll_state) in stm32f4_pll_div_set_rate()
228 struct pll_state { struct248 struct pll_state a; argument249 struct pll_state b;466 struct pll_state *state; in wm8580_set_dai_pll()
