Searched refs:num_context_banks (Results 1 – 4 of 4) sorted by relevance
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()138 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_mmu500_reset()
630 return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); in arm_smmu_alloc_context_bank()1646 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_smmu_device_reset()1830 smmu->num_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMCB, id); in arm_smmu_device_cfg_probe()1831 if (smmu->num_s2_context_banks > smmu->num_context_banks) { in arm_smmu_device_cfg_probe()1836 smmu->num_context_banks, smmu->num_s2_context_banks); in arm_smmu_device_cfg_probe()1837 smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks, in arm_smmu_device_cfg_probe()2174 if (smmu->num_context_banks > smmu->num_context_irqs) { in arm_smmu_device_probe()2177 smmu->num_context_irqs, smmu->num_context_banks); in arm_smmu_device_probe()2182 smmu->num_context_irqs = smmu->num_context_banks; in arm_smmu_device_probe()
216 for (idx = 0; idx < smmu->num_context_banks; idx++) { in nvidia_smmu_context_fault()
300 u32 num_context_banks; member
