Searched refs:irq_ena (Results 1 – 5 of 5) sorted by relevance
103 void __iomem *irq_ena; /* irq enable */ member283 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; in __omap_dm_timer_init_regs()290 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; in __omap_dm_timer_init_regs()377 writel_relaxed(value, timer->irq_ena); in __omap_dm_timer_int_enable()
230 if (dcrtc->irq_ena & mask) { in armada_drm_crtc_disable_irq()231 dcrtc->irq_ena &= ~mask; in armada_drm_crtc_disable_irq()232 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_disable_irq()238 if ((dcrtc->irq_ena & mask) != mask) { in armada_drm_crtc_enable_irq()239 dcrtc->irq_ena |= mask; in armada_drm_crtc_enable_irq()240 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_enable_irq()274 if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) { in armada_drm_crtc_irq()320 v = stat & dcrtc->irq_ena; in armada_drm_irq()929 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; in armada_drm_crtc_create()941 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_create()
63 uint32_t irq_ena; member
40 u8 irq_ena; member397 t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; in dmtimer_systimer_setup()402 t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET; in dmtimer_systimer_setup()529 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); in omap_clockevent_unidle()584 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena); in dmtimer_clockevent_init()
91 writel_relaxed(timer->context.tier, timer->irq_ena); in omap_timer_restore_context()106 timer->context.tier = readl_relaxed(timer->irq_ena); in omap_timer_save_context()656 l = readl_relaxed(timer->irq_ena) & ~mask; in omap_dm_timer_set_int_disable()
