Searched refs:WM_A (Results 1 – 6 of 6) sorted by relevance
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()119 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn3_build_wm_range_table()120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn3_build_wm_range_table()121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_build_wm_range_table()123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_build_wm_range_table()124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()
472 ranges->writer_wm_sets[0].wm_inst = WM_A; in build_watermark_ranges()585 .wm_inst = WM_A,622 .wm_inst = WM_A,659 .wm_inst = WM_A,696 .wm_inst = WM_A,733 .wm_inst = WM_A,
37 #define WM_A 0 macro
43 #define WM_A 0 macro1572 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()1577 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()1584 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()1589 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
2315 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_calculate_wm_and_dlg()2316 …ram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_l… in dcn30_calculate_wm_and_dlg()2317 ….sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter… in dcn30_calculate_wm_and_dlg()2318 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_calculate_wm_and_dlg()2359 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_calculate_wm_and_dlg()
1167 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
