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Searched refs:SDMA_PKT_POLL_REGMEM_DW5_INTERVAL (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dsdma_v2_4.c295 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_hdp_flush()
785 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_pipeline_sync()
811 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_vm_flush()
Dsdma_v3_0.c469 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_hdp_flush()
1056 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_pipeline_sync()
1082 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_vm_flush()
Dsdma_v5_2.c403 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_hdp_flush()
1111 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_pipeline_sync()
1150 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_2_ring_emit_reg_wait()
Dsdma_v5_0.c465 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_hdp_flush()
1165 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_pipeline_sync()
1204 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_0_ring_emit_reg_wait()
Dtonga_sdma_pkt_open.h2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
Diceland_sdma_pkt_open.h2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
Dvega10_sdma_pkt_open.h2511 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
Dsdma_v4_0.c887 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_0_wait_reg_mem()
Dnavi10_sdma_pkt_open.h3835 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro