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Searched refs:PFB (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.10/drivers/video/fbdev/riva/
Dnv_driver.c166 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { in riva_get_memlen()
172 switch (NV_RD32(chip->PFB,0x00000000) & 0x03) { in riva_get_memlen()
190 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { in riva_get_memlen()
204 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) { in riva_get_memlen()
205 memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) * in riva_get_memlen()
208 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) { in riva_get_memlen()
240 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & in riva_get_memlen()
280 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) { in riva_get_maxdclk()
301 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) { in riva_get_maxdclk()
320 par->riva.PFB = in riva_common_setup()
Driva_hw.c816 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv4UpdateArbitrationSettings()
1079 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); in nv10UpdateArbitrationSettings()
1083 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? in nv10UpdateArbitrationSettings()
1317 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); in CalcStateExt()
1407 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1447 NV_WR32(chip->PFB, 0x00000200, state->config); in LoadStateExt()
1544 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); in LoadStateExt()
1545 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); in LoadStateExt()
1561 NV_WR32(chip->PFB, 0x00000240, 0); in LoadStateExt()
1562 NV_WR32(chip->PFB, 0x00000250, 0); in LoadStateExt()
[all …]
Dnvreg.h63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
64 #define PFB_Read(reg) DEVICE_READ(PFB,reg)
65 #define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
66 #define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
67 #define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
68 #define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
Driva_hw.h447 volatile U032 __iomem *PFB; member
/Linux-v5.10/drivers/video/fbdev/nvidia/
Dnv_hw.c391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
634 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0; in nv10UpdateArbitrationSettings()
933 state->config = NV_RD32(par->PFB, 0x00000200); in NVCalcStateExt()
961 NV_WR32(par->PFB, 0x0200, state->config); in NVLoadStateExt()
965 NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0); in NVLoadStateExt()
966 NV_WR32(par->PFB, 0x0244 + (i * 0x10), in NVLoadStateExt()
979 NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0); in NVLoadStateExt()
980 NV_WR32(par->PFB, 0x0604 + (i * 0x10), in NVLoadStateExt()
1205 NV_RD32(&par->PFB[(0x0240 / 4) + i], in NVLoadStateExt()
[all …]
Dnv_setup.c202 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) { in nv4GetConfig()
204 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 + in nv4GetConfig()
207 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) { in nv4GetConfig()
257 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; in nv10GetConfig()
301 par->PFB = par->REGS + (0x00100000 / 4); in NVCommonSetup()
Dnv_type.h159 volatile u32 __iomem *PFB; member