Searched refs:P8 (Results 1 – 13 of 13) sorted by relevance
313 case 1: UNW_DEC_REG_SPREL(P8, UNW_REG_RP, t, arg); break; in unw_decode_p7_p10()314 case 2: UNW_DEC_REG_SPREL(P8, UNW_REG_PFS, t, arg); break; in unw_decode_p7_p10()315 case 3: UNW_DEC_REG_SPREL(P8, UNW_REG_PR, t, arg); break; in unw_decode_p7_p10()316 case 4: UNW_DEC_REG_SPREL(P8, UNW_REG_LC, t, arg); break; in unw_decode_p7_p10()317 case 5: UNW_DEC_REG_SPREL(P8, UNW_REG_UNAT, t, arg); break; in unw_decode_p7_p10()318 case 6: UNW_DEC_REG_SPREL(P8, UNW_REG_FPSR, t, arg); break; in unw_decode_p7_p10()319 case 7: UNW_DEC_REG_WHEN(P8, UNW_REG_BSP, t, arg); break; in unw_decode_p7_p10()320 case 8: UNW_DEC_REG_PSPREL(P8, UNW_REG_BSP, t, arg); break; in unw_decode_p7_p10()321 case 9: UNW_DEC_REG_SPREL(P8, UNW_REG_BSP, t, arg); break; in unw_decode_p7_p10()322 case 10: UNW_DEC_REG_WHEN(P8, UNW_REG_BSPSTORE, t, arg); break; in unw_decode_p7_p10()[all …]
4 Description: Powercap directory for Powernv (P8, P9) servers16 Powernv (P8, P9) servers
125 …PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_…126 …X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PI…127 …AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, …128 …AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32,…129 …AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, B…130 …AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, …
240 pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
209 pins = "P8 GMAC0 TXEN";
82 0x02010208 /* P8 */
3 tristate "Encryption acceleration support on P8 CPU"
83 xargs -0 -P8 -n1 perl -pi -e 'BEGIN {undef $/;}; s/\/\*((?!SPDX).)*?\*\///smg;'
67 s16 P8; member130 enum { P1, P2, P3, P4, P5, P6, P7, P8, P9 }; enumerator197 calib->P8 = le16_to_cpu(p_buf[P8]); in bmp280_read_calib()329 var2 = ((s64)(calib->P8) * p) >> 19; in bmp280_compensate_press()
23 a P8 on-chip bus.
15 the P8, not the POWER processor itself. Communications with the OCC are
16 Endpoints and the implementation on P8 (IODA2). The next two sections talks40 The following section provides a rough description of what we have on P845 2. Implementation of Partitionable Endpoints on P8 (IODA2)48 P8 supports up to 256 Partitionable Endpoints per PHB.
19 The P8 version of this driver is a client driver of I2C. It may be probed
