Home
last modified time | relevance | path

Searched refs:MI_BATCH_BUFFER_END (Results 1 – 21 of 21) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/i915/selftests/
Digt_spinner.c168 *batch++ = MI_BATCH_BUFFER_END; /* not reached */ in igt_spinner_create_request()
205 *spin->batch = MI_BATCH_BUFFER_END; in igt_spinner_end()
Di915_request.c628 *cmd = MI_BATCH_BUFFER_END; in empty_batch()
801 *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */ in recursive_batch()
823 *cmd = MI_BATCH_BUFFER_END; in recursive_batch_resolve()
1075 *cmd = MI_BATCH_BUFFER_END; in live_sequential_engines()
Di915_gem_gtt.c1782 *spinner(batch, i) = MI_BATCH_BUFFER_END; in end_spin()
1836 memset32(batch, MI_BATCH_BUFFER_END, PAGE_SIZE / sizeof(u32)); in igt_cs_tlb()
/Linux-v5.10/drivers/gpu/drm/i915/gt/
Dselftest_engine_cs.c81 cs[0] = MI_BATCH_BUFFER_END; in create_empty_batch()
218 cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END; in create_nop_batch()
Dintel_renderstate.c142 OUT_BATCH(d, i, MI_BATCH_BUFFER_END); in render_state_setup()
Dselftest_ring_submission.c56 *cs++ = MI_BATCH_BUFFER_END; in create_wally()
Dintel_gpu_commands.h57 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) macro
Dselftest_hangcheck.c255 *batch++ = MI_BATCH_BUFFER_END; /* not reached */ in hang_create_request()
290 *h->batch = MI_BATCH_BUFFER_END; in hang_fini()
346 *h.batch = MI_BATCH_BUFFER_END; in igt_hang_sanitycheck()
1483 *h.batch = MI_BATCH_BUFFER_END; in igt_reset_queue()
Dgen7_renderclear.c377 batch_add(&cmds, MI_BATCH_BUFFER_END); in emit_batch()
Dselftest_lrc.c2705 *cs++ = MI_BATCH_BUFFER_END; in create_gang()
3069 *cs++ = MI_BATCH_BUFFER_END; in create_gpr_user()
3638 cs[n] = MI_BATCH_BUFFER_END; in live_preempt_smoke()
4852 } while ((lrc[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in live_lrc_layout()
5598 (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in store_context()
5600 *cs++ = MI_BATCH_BUFFER_END; in store_context()
5758 (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in load_context()
5760 *cs++ = MI_BATCH_BUFFER_END; in load_context()
5910 (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END); in compare_isolation()
Dselftest_workarounds.c577 *cs++ = MI_BATCH_BUFFER_END; in check_dirty_whitelist()
871 *cs++ = MI_BATCH_BUFFER_END; in scrub_whitelisted_registers()
Dselftest_rps.c713 *cancel = MI_BATCH_BUFFER_END; in live_rps_frequency_cs()
853 *cancel = MI_BATCH_BUFFER_END; in live_rps_frequency_srm()
Dintel_lrc.c656 *regs = MI_BATCH_BUFFER_END; in set_offsets()
/Linux-v5.10/drivers/gpu/drm/i915/gem/selftests/
Digt_gem_utils.c85 *cmd = MI_BATCH_BUFFER_END; in igt_emit_store_dw()
Di915_gem_context.c910 *cmd = MI_BATCH_BUFFER_END; in rpcs_query_batch()
1529 *cmd = MI_BATCH_BUFFER_END; in write_to_scratch()
1640 *cmd = MI_BATCH_BUFFER_END; in read_from_scratch()
1674 *cmd = MI_BATCH_BUFFER_END; in read_from_scratch()
Di915_gem_client_blt.c212 *cs++ = MI_BATCH_BUFFER_END; in prepare_blit()
Di915_gem_mman.c1124 bbe = MI_BATCH_BUFFER_END; in __igt_mmap_gpu()
/Linux-v5.10/drivers/gpu/drm/i915/gem/
Di915_gem_object_blt.c95 *cmd = MI_BATCH_BUFFER_END; in intel_emit_vma_fill_blt()
333 *cmd = MI_BATCH_BUFFER_END; in intel_emit_vma_copy_blt()
Di915_gem_execbuffer.c1047 cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END; in reloc_gpu_flush()
/Linux-v5.10/drivers/gpu/drm/i915/
Di915_cmd_parser.c1458 if (*cmd == MI_BATCH_BUFFER_END) in intel_engine_cmd_parser()
1519 *batch_end = MI_BATCH_BUFFER_END; in intel_engine_cmd_parser()
1524 *cmd = MI_BATCH_BUFFER_END; in intel_engine_cmd_parser()
Di915_perf.c1791 *cs++ = MI_BATCH_BUFFER_END; in alloc_noa_wait()