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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h7615 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 macro
Ddce_8_0_sh_mask.h3192 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
Ddce_10_0_sh_mask.h3114 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
Ddce_11_0_sh_mask.h3184 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
Ddce_11_2_sh_mask.h3432 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
Ddce_12_0_sh_mask.h9252 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_sh_mask.h43235 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
Ddcn_1_0_sh_mask.h40001 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
Ddcn_3_0_0_sh_mask.h49112 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
Ddcn_2_0_0_sh_mask.h48744 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro