Searched refs:DP_TRAINING_PATTERN_1 (Results 1 – 15 of 15) sorted by relevance
530 case DP_TRAINING_PATTERN_1: in drm_dp_link_train_wait()617 link->train.pattern = DP_TRAINING_PATTERN_1; in drm_dp_link_clock_recovery()795 link->train.pattern = DP_TRAINING_PATTERN_1; in drm_dp_link_train_fast()
828 case DP_TRAINING_PATTERN_1: in tegra_sor_dp_link_apply_training()
571 case DP_TRAINING_PATTERN_1: in radeon_dp_set_tp()584 case DP_TRAINING_PATTERN_1: in radeon_dp_set_tp()671 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); in radeon_dp_link_train_cr()
519 case DP_TRAINING_PATTERN_1: in amdgpu_atombios_dp_set_tp()602 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); in amdgpu_atombios_dp_link_train_cr()
193 DP_TRAINING_PATTERN_1 | in intel_dp_link_training_clock_recovery()
3785 case DP_TRAINING_PATTERN_1: in cpt_set_link_train()3815 case DP_TRAINING_PATTERN_1: in g4x_set_link_train()3839 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); in intel_dp_enable_port()
4171 case DP_TRAINING_PATTERN_1: in intel_ddi_set_link_train()
599 edp_host_train_set(ctrl, DP_TRAINING_PATTERN_1); in edp_start_link_train_1()604 DP_TRAINING_PATTERN_1 | DP_RECOVERED_CLOCK_OUT_EN); in edp_start_link_train_1()
700 DP_TRAINING_PATTERN_1); in zynqmp_dp_link_train_cr()702 DP_TRAINING_PATTERN_1 | in zynqmp_dp_link_train_cr()
1514 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) { in cdv_intel_dp_start_link_train()1520 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1); in cdv_intel_dp_start_link_train()
1094 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); in dp_ctrl_link_train_1()1097 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | in dp_ctrl_link_train_1()
443 # define DP_TRAINING_PATTERN_1 1 macro
1021 DP_TRAINING_PATTERN_1); in tc_main_link_enable()
311 DP_TRAINING_PATTERN_1); in analogix_dp_link_start()
904 DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE); in cdns_mhdp_link_training_init()
