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Searched refs:ADF_CSR_WR (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.10/drivers/crypto/qat/qat_common/
Dadf_transport_access_macros.h87 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
94 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
96 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
100 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
103 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
106 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
110 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
112 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
116 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
119 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
[all …]
Dadf_pf2vf_msg.c21 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x0); in adf_enable_pf2vf_interrupts()
31 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x2); in adf_disable_pf2vf_interrupts()
47 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); in adf_enable_vf2pf_interrupts()
54 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); in adf_enable_vf2pf_interrupts()
70 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); in adf_disable_vf2pf_interrupts()
77 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); in adf_disable_vf2pf_interrupts()
126 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg); in __adf_iov_putmsg()
145 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg | int_bit); in __adf_iov_putmsg()
160 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, val & ~local_in_use_mask); in __adf_iov_putmsg()
205 ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg); in adf_vf2pf_req_hndl()
Dadf_hw_arbiter.c19 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
23 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
27 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
32 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
Dicp_qat_hal.h91 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
101 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
109 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
111 ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
Dadf_admin.c132 ADF_CSR_WR(mailbox, mb_offset, 1); in adf_put_admin_msg_sync()
258 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32); in adf_init_admin_comms()
259 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val); in adf_init_admin_comms()
Dadf_sriov.c27 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \
35 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
Dadf_vf_isr.c108 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); in adf_pf2vf_bh_handler()
128 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); in adf_pf2vf_bh_handler()
Dadf_accel_devices.h148 #define ADF_CSR_WR(csr_base, csr_offset, val) \ macro
Dqat_hal.c425 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
/Linux-v5.10/drivers/crypto/qat/qat_c3xxx/
Dadf_c3xxx_hw_data.c119 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
122 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
129 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); in adf_enable_error_correction()
132 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val); in adf_enable_error_correction()
143 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
145 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
/Linux-v5.10/drivers/crypto/qat/qat_c62x/
Dadf_c62x_hw_data.c129 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
132 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
139 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); in adf_enable_error_correction()
142 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val); in adf_enable_error_correction()
153 ADF_CSR_WR(addr, ADF_C62X_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
155 ADF_CSR_WR(addr, ADF_C62X_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
/Linux-v5.10/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c141 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
144 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
151 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction()
154 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction()
165 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
168 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET, in adf_enable_ints()